1 //==============================================================================
2 // Copyright 2011 Meta Watch Ltd. - http://www.MetaWatch.org/
4 // Licensed under the Meta Watch License, Version 1.0 (the "License");
5 // you may not use this file except in compliance with the License.
6 // You may obtain a copy of the License at
8 // http://www.MetaWatch.org/licenses/license-1.0.html
10 // Unless required by applicable law or agreed to in writing, software
11 // distributed under the License is distributed on an "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 // See the License for the specific language governing permissions and
14 // limitations under the License.
15 //==============================================================================
17 /******************************************************************************/
18 /*! \file hal_devboard_v2_defs.h
20 * Pin and peripheral definitions for Development Board Version 2
22 /******************************************************************************/
25 #ifndef HAL_DEVBOARD_V2_DEFS_H
26 #define HAL_DEVBOARD_V2_DEFS_H
29 // Defines for the LCD display interface, single channel SPI output
30 #define LCD_5V_PDIR P4DIR
31 #define LCD_5V_POUT P4OUT
32 #define LCD_5V_BIT BIT0
34 #define ENABLE_LCD_POWER() { \
35 LCD_5V_PDIR |= LCD_5V_BIT; \
36 LCD_5V_POUT |= LCD_5V_BIT; \
39 #define DISABLE_LCD_POWER() { \
40 LCD_5V_PDIR |= LCD_5V_BIT; \
41 LCD_5V_POUT &= ~LCD_5V_BIT; \
44 #define LCD_ENABLE_PDIR ( P3DIR )
45 #define LCD_ENABLE_POUT ( P3OUT )
46 #define LCD_ENABLE_PIN ( BIT6 )
48 #define ENABLE_LCD_ENABLE() { \
49 LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
50 LCD_ENABLE_POUT |= LCD_ENABLE_PIN; \
53 #define DISABLE_LCD_ENABLE() { \
54 LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
55 LCD_ENABLE_POUT &= ~LCD_ENABLE_PIN; \
58 #define LCD_CS_PDIR ( P9DIR )
59 #define LCD_CS_POUT ( P9OUT )
60 #define LCD_CS_PIN ( BIT0 )
62 #define LCD_SPI_PORT_SEL ( P3SEL )
63 #define LCD_SPI_SIMO_BIT ( BIT1 )
64 #define LCD_SPI_CLK_BIT ( BIT3 )
65 #define LCD_SPI_SOMI_BIT ( BIT2 )
67 #define LCD_CS_ASSERT() { LCD_CS_POUT |= LCD_CS_PIN; }
68 #define LCD_CS_DEASSERT() { LCD_CS_POUT &= ~LCD_CS_PIN; }
70 #define CONFIG_LCD_PINS() { \
71 LCD_SPI_PORT_SEL |= LCD_SPI_SIMO_BIT; \
72 LCD_SPI_PORT_SEL |= LCD_SPI_CLK_BIT; \
73 LCD_SPI_PORT_SEL |= LCD_SPI_SOMI_BIT; \
74 ENABLE_LCD_ENABLE(); \
75 LCD_CS_PDIR |= LCD_CS_PIN; \
79 // labeled EL_EN on schematic
80 #define LCD_LED_PDIR ( P4DIR )
81 #define LCD_LED_POUT ( P4OUT )
82 #define LCD_LED_PIN ( BIT4 )
84 #define DISABLE_LCD_LED() { \
85 LCD_LED_PDIR |= LCD_LED_PIN; \
86 LCD_LED_POUT &= ~LCD_LED_PIN; \
89 #define ENABLE_LCD_LED() { \
90 LCD_LED_PDIR |= LCD_LED_PIN; \
91 LCD_LED_POUT |= LCD_LED_PIN; \
94 #define LCD_SPI_UCBxCTL0 UCB0CTL0 // Control register
95 #define LCD_SPI_UCBxCTL1 UCB0CTL1 // Control register
96 #define LCD_SPI_UCBxBR0 UCB0BR0 // Baudrate prescale
97 #define LCD_SPI_UCBxBR1 UCB0BR1 // Baudrate divider
99 #define LCD_SPI_UCBxTXBUF UCB0TXBUF // Transmit buffer
100 #define LCD_SPI_UCBxRXBUF UCB0RXBUF // Receive buffer
102 #define LCD_SPI_UCBxIE UCB0IE // Interrupt enable register
103 #define LCD_SPI_UCBxIFG UCB0IFG // Interrupt flag register
104 #define LCD_SPI_UCBxIV UCB0IV // Interrupt vector register
105 #define LCD_SPI_UCBxSTAT UCB0STAT // status register
108 // Definitions for the OLED Display
109 // peripheral mapping for OLED
110 #define OLED_I2C_CTL0 ( UCB0CTL0 )
111 #define OLED_I2C_CTL1 ( UCB0CTL1 )
112 #define OLED_I2C_BR0 ( UCB0BR0 )
113 #define OLED_I2C_BR1 ( UCB0BR1 )
114 #define OLED_I2C_I2CSA ( UCB0I2CSA )
115 #define OLED_I2C_IE ( UCB0IE )
116 #define OLED_I2C_IFG ( UCB0IFG )
117 #define OLED_I2C_TXBUF ( UCB0TXBUF )
118 #define OLED_I2C_RXBUF ( UCB0RXBUF )
119 // interrupt mapping for OLED
120 #define USCI_OLED_I2C_VECTOR ( USCI_B0_VECTOR )
121 #define USCI_OLED_I2C_IV ( UCB0IV )
123 // OLED reset is active low
124 #define OLED_RSTN_PDIR ( P8DIR )
125 #define OLED_RSTN_POUT ( P8OUT )
126 #define OLED_RSTN_PIN ( BIT7 )
128 #define OLED_RSTN_CONFIG() { OLED_RSTN_PDIR |= OLED_RSTN_PIN; OLED_RSTN_ASSERT(); }
129 #define OLED_RSTN_ASSERT() { OLED_RSTN_POUT &= ~OLED_RSTN_PIN; }
130 #define OLED_RSTN_DEASSERT() { OLED_RSTN_POUT |= OLED_RSTN_PIN; }
132 #define OLED_CS1N_PDIR ( P8DIR )
133 #define OLED_CS1N_POUT ( P8OUT )
134 #define OLED_CS1N_PIN ( BIT0 )
136 #define OLED_CS1N_CONFIG() { OLED_CS1N_PDIR |= OLED_CS1N_PIN; OLED_CS1N_DISABLE(); }
137 #define OLED_CS1N_ENABLE() { OLED_CS1N_POUT &= ~OLED_CS1N_PIN; }
138 #define OLED_CS1N_DISABLE() { OLED_CS1N_POUT |= OLED_CS1N_PIN; }
140 #define OLED_CS2N_PDIR ( P8DIR )
141 #define OLED_CS2N_POUT ( P8OUT )
142 #define OLED_CS2N_PIN ( BIT1 )
144 #define OLED_CS2N_CONFIG() { OLED_CS2N_PDIR |= OLED_CS2N_PIN; OLED_CS2N_DISABLE(); }
145 #define OLED_CS2N_ENABLE() { OLED_CS2N_POUT &= ~OLED_CS2N_PIN; }
146 #define OLED_CS2N_DISABLE() { OLED_CS2N_POUT |= OLED_CS2N_PIN; }
148 #define OLED_SDA_PDIR ( P3DIR )
149 #define OLED_SDA_POUT ( P3OUT )
150 #define OLED_SDA_PIN ( BIT1 )
151 #define OLED_SDA_PSEL ( P3SEL)
153 #define OLED_SCL_PDIR ( P3DIR )
154 #define OLED_SCL_POUT ( P3OUT )
155 #define OLED_SCL_PORT ( P3 )
156 #define OLED_SCL_PIN ( BIT2 )
157 #define OLED_SCL_PSEL ( P3SEL )
159 // the select line overrides the pdir and pout settings
160 #define OLED_SDA_CONFIG_FOR_PERIPHERAL_USE() { OLED_SDA_PSEL |= OLED_SDA_PIN; }
161 #define OLED_SCL_CONFIG_FOR_PERIPHERAL_USE() { OLED_SCL_PSEL |= OLED_SCL_PIN; }
163 #define OLED_I2C_CONFIG_FOR_PERIPHERAL_USE() { \
164 OLED_SDA_CONFIG_FOR_PERIPHERAL_USE(); \
165 OLED_SCL_CONFIG_FOR_PERIPHERAL_USE(); }
167 #define OLED_SDA_CONFIG_FOR_SLEEP() { \
168 OLED_SDA_PSEL &= ~OLED_SDA_PIN; \
169 OLED_SDA_PDIR |= OLED_SDA_PIN; \
170 OLED_SDA_POUT |= OLED_SDA_PIN; }
172 #define OLED_SCL_CONFIG_FOR_SLEEP() { \
173 OLED_SCL_PSEL &= ~OLED_SCL_PIN; \
174 OLED_SCL_PDIR |= OLED_SCL_PIN; \
175 OLED_SCL_POUT |= OLED_SCL_PIN; }
177 #define OLED_I2C_CONFIG_FOR_SLEEP() { \
178 OLED_SDA_CONFIG_FOR_SLEEP(); \
179 OLED_SCL_CONFIG_FOR_SLEEP(); }
181 #define OLED_POWER_ENABLE_PIN ( BIT0 )
182 #define OLED_POWER_ENABLE_POUT ( P4OUT )
183 #define OLED_POWER_ENABLE_PDIR ( P4DIR )
184 #define OLED_POWER_CONFIG() { P4DIR |= OLED_POWER_ENABLE_PIN; OLED_POWER_DISABLE(); }
185 #define OLED_POWER_ENABLE() { P4OUT |= OLED_POWER_ENABLE_PIN; }
186 #define OLED_POWER_DISABLE() { P4OUT &= ~OLED_POWER_ENABLE_PIN; }
188 // VLED_EN is active low
189 #define OLED_IO_POWER_ENABLE_PIN ( BIT3 )
190 #define OLED_IO_POWER_ENABLE_POUT ( P5OUT )
191 #define OLED_IO_POWER_ENABLE_PDIR ( P5DIR )
192 #define OLED_IO_POWER_CONFIG() { P5DIR |= OLED_IO_POWER_ENABLE_PIN; OLED_IO_POWER_DISABLE(); }
193 #define OLED_IO_POWER_ENABLE() { P5OUT &= ~OLED_IO_POWER_ENABLE_PIN; }
194 #define OLED_IO_POWER_DISABLE() { P5OUT |= OLED_IO_POWER_ENABLE_PIN; }
197 #define CONFIG_OLED_PINS() { \
198 OLED_RSTN_CONFIG(); \
199 OLED_CS1N_CONFIG(); \
200 OLED_CS2N_CONFIG(); \
201 OLED_POWER_CONFIG(); \
202 OLED_I2C_CONFIG_FOR_SLEEP(); \
203 OLED_IO_POWER_CONFIG(); \
206 /* jumpers for 10V must be removed for power consumption measurements */
207 #define CONFIG_OLED_PINS() { \
208 OLED_RSTN_CONFIG(); \
209 OLED_CS1N_CONFIG(); \
210 OLED_CS1N_ENABLE(); \
211 OLED_CS2N_CONFIG(); \
212 OLED_CS2N_ENABLE(); \
213 OLED_POWER_CONFIG(); \
214 OLED_IO_POWER_CONFIG(); \
219 // Real time clock defines
220 // RTC 1 Hz output, also used to toggle the bias on the LCD
221 #define RTC_1HZ_PORT_DIR ( P2DIR )
222 #define RTC_1HZ_PORT_SEL ( P2SEL )
223 #define RTC_1HZ_BIT ( BIT4 )
228 #define BUTTON_TIME_COUNT_ARRAY_LEN 8
229 #define ALL_BUTTONS_OFF 0xFF
240 #define SW_A_INDEX ( 0 )
241 #define SW_B_INDEX ( 1 )
242 #define SW_C_INDEX ( 2 )
243 #define SW_D_INDEX ( 3 )
244 #define SW_UNUSED_INDEX ( 4 )
245 #define SW_E_INDEX ( 5 )
246 #define SW_F_INDEX ( 6 )
247 #define SW_P_INDEX ( 7 )
248 #define TOTAL_BTN_NUM ( 8 )
251 /* analog board has traces for all of the buttons but
252 * only 3 and pull switch are populated */
253 #define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_P)
255 #elif defined(DIGITAL)
257 #define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_D | SW_E | SW_F)
261 #define RESISTOR_ENABLE_BUTTONS ( ALL_BUTTONS )
262 #define INT_EDGE_SEL_BUTTONS (ALL_BUTTONS)
264 #define BUTTON_PORT_VECTOR PORT2_VECTOR
265 #define BUTTON_PORT_DIR P2DIR
266 #define BUTTON_PORT_SEL P2SEL
267 #define BUTTON_PORT_OUT P2OUT
268 #define BUTTON_PORT_REN P2REN
269 #define BUTTON_PORT_IE P2IE
270 #define BUTTON_PORT_IES P2IES
271 #define BUTTON_PORT_IFG P2IFG
273 #define DISABLE_BUTTONS() { \
274 BUTTON_PORT_IE &= ~INT_EDGE_SEL_BUTTONS; \
275 BUTTON_PORT_REN &= ~ALL_BUTTONS; \
276 BUTTON_PORT_OUT &= ~ALL_BUTTONS; \
280 /* S5 or SW_E is the button that takes the watch out of shipping mode */
281 #define ENABLE_SHIPPING_WAKEUP() { \
285 RTCPS0CTL = 0x0000; \
286 RTCPS1CTL = 0x0000; \
288 BUTTON_PORT_REN = SW_E; \
289 BUTTON_PORT_OUT = SW_E; \
290 BUTTON_PORT_DIR &= ~SW_E; \
291 BUTTON_PORT_IES = SW_E; \
292 BUTTON_PORT_IFG = 0x00; \
293 BUTTON_PORT_IE = SW_E; \
296 // NOTE the the buttons are grounded. That means that we want to invert the bits
297 // when reading the port to have positive logic where a button press is a "1"
298 #define BUTTON_PORT_IN ~P2IN
300 // Configure the hardware port for the button support P2.4 is excluded
301 #define CONFIGURE_BUTTON_PINS() { \
302 BUTTON_PORT_REN = (unsigned char) RESISTOR_ENABLE_BUTTONS; \
303 BUTTON_PORT_OUT = (unsigned char) ALL_BUTTONS; \
304 BUTTON_PORT_DIR &= (unsigned char) ~ALL_BUTTONS; \
305 BUTTON_PORT_IES |= INT_EDGE_SEL_BUTTONS; \
306 BUTTON_PORT_IFG &= ~ALL_BUTTONS; \
307 BUTTON_PORT_IE |= ALL_BUTTONS; \
311 // Battery charger control for a BQ24080
312 #define BAT_CHARGE_DIR P6DIR
313 #define BAT_CHARGE_REN P6REN
314 #define BAT_CHARGE_OUT P6OUT
315 #define BAT_CHARGE_IN P6IN
316 //#define BAT_CHARGE_IE P6IE
317 //#define PWR_PORT_VECTOR PORT6_VECTOR
318 //#define PWR_PORT_IFG P6IFG
320 #define BAT_CHARGE_ENABLE_PIN BIT2
321 #define BAT_CHARGE_STAT1 BIT3
322 #define BAT_CHARGE_STAT2 BIT4
323 #define BAT_CHARGE_PWR_BIT BIT5
325 // Enable charging, asserted low
326 #define BATTERY_CHARGE_ENABLE() { BAT_CHARGE_OUT &= ~BAT_CHARGE_ENABLE_PIN; }
328 // disable charging, sleep the part
329 #define BATTERY_CHARGE_DISABLE() { BAT_CHARGE_OUT |= BAT_CHARGE_ENABLE_PIN; }
331 //RESET PIN NMI or RESET
332 #define SET_RESET_PIN_NMI() {SFRRPCR &= ~SYSRSTRE; SFRRPCR |= SYSNMI;}
333 #define SET_RESET_PIN_RST() {SFRRPCR |= SYSRSTRE; SFRRPCR &= ~SYSNMI;}
334 #define RESET_PIN (SFRRPCR & SYSNMI) // return 1 for NMI
337 // Ambient Light Sensor
339 #define GC1_PDIR ( P6DIR )
340 #define GC1_POUT ( P6OUT )
341 #define GC1_PSEL ( P6SEL )
342 #define GC1_PIN ( BIT0 )
344 #define GC2_PDIR ( P6DIR )
345 #define GC2_POUT ( P6OUT )
346 #define GC2_PSEL ( P6SEL )
347 #define GC2_PIN ( BIT6 )
349 #define IOUT_PDIR ( P6DIR )
350 #define IOUT_PSEL ( P6SEL )
351 #define IOUT_PIN ( BIT1 )
353 #define LIGHT_SENSE_INIT() \
355 IOUT_PDIR &= ~IOUT_PIN; \
356 IOUT_PSEL |= IOUT_PIN; \
357 GC1_PDIR |= GC1_PIN; \
358 GC2_PDIR |= GC2_PIN; \
359 LIGHT_SENSE_DISABLE(); \
362 #define LIGHT_SENSOR_SHUTDOWN() \
364 GC1_POUT &= ~GC1_PIN; \
365 GC2_POUT &= ~GC2_PIN; \
368 #define LIGHT_SENSOR_L_GAIN() \
370 GC1_POUT |= GC1_PIN; \
371 GC2_POUT |= GC2_PIN; \
374 #define LIGHT_SENSE_ENABLE()\
376 LIGHT_SENSOR_L_GAIN(); \
379 #define LIGHT_SENSE_DISABLE() \
381 LIGHT_SENSOR_SHUTDOWN(); \
387 // This pin controls if the battery voltage can be read
389 #define BATTERY_READ_CONTROL_PDIR ( P4DIR )
390 #define BATTERY_READ_CONTROL_POUT ( P4OUT )
391 #define BATTERY_READ_CONTROL_PIN ( BIT6 )
393 #define BATTERY_SENSE_INPUT_PDIR ( P7DIR )
394 #define BATTERY_SENSE_INPUT_PSEL ( P7SEL )
395 #define BATTERY_SENSE_INPUT_PIN ( BIT7 )
397 #define BATTERY_SENSE_INIT() \
399 BATTERY_READ_CONTROL_PDIR |= BATTERY_READ_CONTROL_PIN; \
400 BATTERY_SENSE_INPUT_PDIR &= ~BATTERY_SENSE_INPUT_PIN; \
401 BATTERY_SENSE_INPUT_PSEL |= BATTERY_SENSE_INPUT_PIN; \
402 BATTERY_SENSE_DISABLE(); \
405 #define BATTERY_SENSE_ENABLE() \
407 BATTERY_READ_CONTROL_POUT |= BATTERY_READ_CONTROL_PIN; \
410 #define BATTERY_SENSE_DISABLE() \
412 BATTERY_READ_CONTROL_POUT &= ~BATTERY_READ_CONTROL_PIN; \
416 // hardware configuration is a voltage divider to ADC input
418 #define HARDWARE_CFG_CONTROL_PDIR ( P5DIR )
419 #define HARDWARE_CFG_CONTROL_POUT ( P5OUT )
420 #define HARDWARE_CFG_CONTROL_PIN ( BIT0 )
422 #define HARDWARE_CFG_INPUT_PDIR ( P7DIR )
423 #define HARDWARE_CFG_INPUT_PSEL ( P7SEL )
424 #define HARDWARE_CFG_INPUT_PIN ( BIT5 )
426 #define HARDWARE_CFG_SENSE_INIT() \
428 HARDWARE_CFG_CONTROL_PDIR |= HARDWARE_CFG_CONTROL_PIN; \
429 HARDWARE_CFG_INPUT_PDIR &= ~HARDWARE_CFG_INPUT_PIN; \
430 HARDWARE_CFG_INPUT_PSEL |= HARDWARE_CFG_INPUT_PIN; \
431 HARDWARE_CFG_SENSE_DISABLE(); \
434 #define HARDWARE_CFG_SENSE_ENABLE() \
436 HARDWARE_CFG_CONTROL_POUT |= HARDWARE_CFG_CONTROL_PIN; \
439 #define HARDWARE_CFG_SENSE_DISABLE() \
441 HARDWARE_CFG_CONTROL_POUT &= ~HARDWARE_CFG_CONTROL_PIN; \
445 #define APPLE_SDA_PDIR ( P10DIR )
446 #define APPLE_SDA_POUT ( P10OUT )
447 #define APPLE_SDA_PIN ( BIT1 )
449 #define APPLE_SCL_PDIR ( P10DIR )
450 #define APPLE_SCL_POUT ( P10OUT )
451 #define APPLE_SCL_PIN ( BIT2 )
453 #define APPLE_POWER_PDIR ( P4DIR )
454 #define APPLE_POWER_POUT ( P4OUT )
455 #define APPLE_POWER_PIN ( BIT5 )
457 /* power enable is active low */
458 #define APPLE_POWER_ENABLE() { APPLE_POWER_POUT &= ~APPLE_POWER_PIN; }
459 #define APPLE_POWER_DISABLE() { APPLE_POWER_POUT |= APPLE_POWER_PIN; }
461 #define APPLE_POWER_CONFIG() { \
462 APPLE_POWER_PDIR |= APPLE_POWER_PIN; \
463 APPLE_POWER_DISABLE(); \
467 /* since the apple chip is currently not powered
468 * the pins should be at 0 instead of 1
470 #define APPLE_I2C_PIN_CONFIG() { \
471 APPLE_SDA_PDIR |= APPLE_SDA_PIN; \
472 APPLE_SDA_POUT &= ~APPLE_SDA_PIN; \
473 APPLE_SCL_PDIR |= APPLE_SCL_PIN; \
474 APPLE_SCL_POUT &= ~APPLE_SCL_PIN; \
477 #define APPLE_CONFIG() { \
478 APPLE_POWER_CONFIG(); \
479 APPLE_I2C_PIN_CONFIG(); \
482 #define SRAM_SCLK_PSEL ( P3SEL )
483 #define SRAM_SCLK_PDIR ( P3DIR )
484 #define SRAM_SCLK_POUT ( P3OUT )
485 #define SRAM_SCLK_PIN ( BIT0 )
487 #define SRAM_SOMI_PSEL ( P3SEL )
488 #define SRAM_SOMI_PDIR ( P3DIR )
489 #define SRAM_SOMI_POUT ( P3OUT )
490 #define SRAM_SOMI_PIN ( BIT5 )
492 #define SRAM_SIMO_PSEL ( P3SEL )
493 #define SRAM_SIMO_PDIR ( P3DIR )
494 #define SRAM_SIMO_POUT ( P3OUT )
495 #define SRAM_SIMO_PIN ( BIT4 )
497 #define SRAM_CSN_PDIR ( P9DIR )
498 #define SRAM_CSN_POUT ( P9OUT )
499 #define SRAM_CSN_PIN ( BIT6)
501 #define SRAM_HOLDN_PDIR ( P9DIR )
502 #define SRAM_HOLDN_POUT ( P9OUT )
503 #define SRAM_HOLDN_PIN ( BIT7 )
505 #define CONFIG_SRAM_PINS() \
507 SRAM_CSN_PDIR |= SRAM_CSN_PIN; \
508 SRAM_CSN_POUT |= SRAM_CSN_PIN; \
509 SRAM_HOLDN_PDIR |= SRAM_HOLDN_PIN; \
510 SRAM_HOLDN_POUT |= SRAM_HOLDN_PIN; \
513 #define SRAM_CSN_ASSERT() { SRAM_CSN_POUT &= ~SRAM_CSN_PIN; }
515 #define SRAM_CSN_DEASSERT() { \
516 WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE(); \
517 SRAM_CSN_POUT |= SRAM_CSN_PIN; \
520 /* wait for shift to complete ( ~3 us ) */
521 #define WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE() { while( (UCA0STAT & 0x01) != 0 ); }
523 #define ACCELEROMETER_SDA_PIN ( BIT7 )
524 #define ACCELEROMETER_SDA_PSEL ( P3SEL )
525 #define ACCELEROMETER_SDA_POUT ( P3OUT )
526 #define ACCELEROMETER_SDA_PDIR ( P3OUT )
527 #define ACCELEROMETER_SDA_PREN ( P1REN )
529 #define ACCELEROMETER_SCL_PIN ( BIT4 )
530 #define ACCELEROMETER_SCL_PSEL ( P5SEL )
531 #define ACCELEROMETER_SCL_POUT ( P5OUT )
532 #define ACCELEROMETER_SCL_PDIR ( P5OUT )
533 #define ACCELEROMETER_SCL_PREN ( P5REN )
535 #define ACCELEROMETER_INT_PIN ( BIT7 )
536 #define ACCELEROMETER_INT_PDIR ( P1DIR )
537 #define ACCELEROMETER_INT_PSEL ( P1SEL )
538 #define ACCELEROMETER_INT_PIFG ( P1IFG )
539 #define ACCELEROMETER_INT_PIE ( P1IE )
541 #define ACCELEROMETER_POWER_POUT ( P9OUT )
542 #define ACCELEROMETER_POWER_PDIR ( P9DIR )
543 #define ACCELEROMETER_POWER_PINS ( BIT1 | BIT2 )
545 /* this is for reference only (it doesn't control anything) */
546 #define ACCELEROMETER_INT_NUM (PIN7_INT)
548 #define LED4_PIN ( BIT2 )
549 #define LED5_PIN ( BIT3 )
550 #define LED6_PIN ( BIT4 )
551 #define LED7_PIN ( BIT5 )
553 #define LEDS_PDIR ( P8DIR )
554 #define LEDS_POUT ( P8OUT )
556 #define LED4_ON() { LEDS_POUT |= LED4_PIN; }
557 #define LED5_ON() { LEDS_POUT |= LED5_PIN; }
558 #define LED6_ON() { LEDS_POUT |= LED6_PIN; }
559 #define LED7_ON() { LEDS_POUT |= LED7_PIN; }
561 #define LED4_OFF() { LEDS_POUT &= ~LED4_PIN; }
562 #define LED5_OFF() { LEDS_POUT &= ~LED5_PIN; }
563 #define LED6_OFF() { LEDS_POUT &= ~LED6_PIN; }
564 #define LED7_OFF() { LEDS_POUT &= ~LED7_PIN; }
566 #define LED4_TOGGLE() { LEDS_POUT ^= LED4_PIN; }
567 #define LED5_TOGGLE() { LEDS_POUT ^= LED5_PIN; }
568 #define LED6_TOGGLE() { LEDS_POUT ^= LED6_PIN; }
569 #define LED7_TOGGLE() { LEDS_POUT ^= LED7_PIN; }
571 #define CONFIG_LED_PINS() { \
572 LEDS_PDIR |= LED4_PIN | LED5_PIN | LED6_PIN | LED7_PIN; \
573 LED4_OFF(); LED5_OFF(); LED6_OFF(); LED7_OFF(); \
576 #define DEBUG1_PIN ( BIT1 )
577 #define DEBUG3_PIN ( BIT4 )
578 #define DEBUG4_PIN ( BIT7 )
579 #define DEBUG5_PIN ( BIT6 )
581 #define DEBUG1_PDIR ( P5DIR )
582 #define DEBUG3_PDIR ( P7DIR )
583 #define DEBUG4_PDIR ( P6DIR )
584 #define DEBUG5_PDIR ( P7DIR )
586 #define DEBUG1_POUT ( P5OUT )
587 #define DEBUG3_POUT ( P7OUT )
588 #define DEBUG4_POUT ( P6OUT )
589 #define DEBUG5_POUT ( P7OUT )
591 #define DEBUG1_HIGH() { DEBUG1_POUT |= DEBUG1_PIN; }
592 #define DEBUG3_HIGH() { DEBUG3_POUT |= DEBUG3_PIN; }
593 #define DEBUG4_HIGH() { DEBUG4_POUT |= DEBUG4_PIN; }
594 #define DEBUG5_HIGH() { DEBUG5_POUT |= DEBUG5_PIN; }
596 #define DEBUG1_LOW() { DEBUG1_POUT &= ~DEBUG1_PIN; }
597 #define DEBUG3_LOW() { DEBUG3_POUT &= ~DEBUG3_PIN; }
598 #define DEBUG4_LOW() { DEBUG4_POUT &= ~DEBUG4_PIN; }
599 #define DEBUG5_LOW() { DEBUG5_POUT &= ~DEBUG5_PIN; }
601 #define DEBUG1_PULSE() { DEBUG1_HIGH(); DEBUG1_LOW(); }
602 #define DEBUG3_PULSE() { DEBUG3_HIGH(); DEBUG3_LOW(); }
603 #define DEBUG4_PULSE() { DEBUG4_HIGH(); DEBUG4_LOW(); }
604 #define DEBUG5_PULSE() { DEBUG5_HIGH(); DEBUG5_LOW(); }
606 #define DEBUG1_TOGGLE() { DEBUG1_POUT ^= DEBUG1_PIN; }
607 #define DEBUG3_TOGGLE() { DEBUG3_POUT ^= DEBUG3_PIN; }
608 #define DEBUG4_TOGGLE() { DEBUG4_POUT ^= DEBUG4_PIN; }
609 #define DEBUG5_TOGGLE() { DEBUG5_POUT ^= DEBUG5_PIN; }
611 #define CONFIG_DEBUG_PINS() { \
612 DEBUG1_PDIR |= DEBUG1_PIN; \
613 DEBUG3_PDIR |= DEBUG3_PIN; \
614 DEBUG4_PDIR |= DEBUG4_PIN; \
615 DEBUG5_PDIR |= DEBUG5_PIN; \
616 DEBUG1_POUT &= ~DEBUG1_PIN; \
617 DEBUG3_POUT &= ~DEBUG3_PIN; \
618 DEBUG4_POUT &= ~DEBUG4_PIN; \
619 DEBUG5_POUT &= ~DEBUG5_PIN; \
625 * Sideband signals (for lack of another word)
627 #define BT_CLK_REQ_PDIR ( P1DIR )
628 #define BT_CLK_REQ_POUT ( P1OUT )
629 #define BT_CLK_REQ_PIN ( BIT4 )
631 #define BT_IO1_PDIR ( P1DIR )
632 #define BT_IO1_POUT ( P1OUT )
633 #define BT_IO1_PIN ( BIT5 )
635 #define BT_IO2_PDIR ( P1DIR )
636 #define BT_IO2_POUT ( P1OUT )
637 #define BT_IO2_PIN ( BIT6 )
639 /******************************************************************************/
641 /* peripheral mapping for accelerometer */
642 #define ACCELEROMETER_CTL0 ( UCB1CTL0 )
643 #define ACCELEROMETER_CTL1 ( UCB1CTL1 )
644 #define ACCELEROMETER_BR0 ( UCB1BR0 )
645 #define ACCELEROMETER_BR1 ( UCB1BR1 )
646 #define ACCELEROMETER_I2CSA ( UCB1I2CSA )
647 #define ACCELEROMETER_IE ( UCB1IE )
648 #define ACCELEROMETER_IFG ( UCB1IFG )
649 #define ACCELEROMETER_TXBUF ( UCB1TXBUF )
650 #define ACCELEROMETER_RXBUF ( UCB1RXBUF )
651 #define ACCELEROMETER_STAT ( UCB1STAT )
652 /* interrupt mapping for accelerometer */
653 #define USCI_ACCELEROMETER_VECTOR ( USCI_B1_VECTOR )
654 #define USCI_ACCELEROMETER_IV ( UCB1IV )
659 #endif // HAL_DEVBOARD_V2_DEFS_H