1 //==============================================================================
2 // Copyright 2011 Meta Watch Ltd. - http://www.MetaWatch.org/
4 // Licensed under the Meta Watch License, Version 1.0 (the "License");
5 // you may not use this file except in compliance with the License.
6 // You may obtain a copy of the License at
8 // http://www.MetaWatch.org/licenses/license-1.0.html
10 // Unless required by applicable law or agreed to in writing, software
11 // distributed under the License is distributed on an "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 // See the License for the specific language governing permissions and
14 // limitations under the License.
15 //==============================================================================
17 /******************************************************************************/
18 /*! \file hal_digital_v2_defs.h
20 * Pin and peripheral definitions for Digital Watch Version 2
22 /******************************************************************************/
24 #ifndef HAL_DIGITAL_V2_DEFS_H
25 #define HAL_DIGITAL_V2_DEFS_H
28 // Defines for the LCD display interface, single channel SPI output
29 #define LCD_5V_PDIR P4DIR
30 #define LCD_5V_POUT P4OUT
31 #define LCD_5V_BIT BIT0
33 #define ENABLE_LCD_POWER() { \
34 LCD_5V_PDIR |= LCD_5V_BIT; \
35 LCD_5V_POUT |= LCD_5V_BIT; \
38 #define DISABLE_LCD_POWER() { \
39 LCD_5V_PDIR |= LCD_5V_BIT; \
40 LCD_5V_POUT &= ~LCD_5V_BIT; \
43 #define LCD_ENABLE_PDIR ( P3DIR )
44 #define LCD_ENABLE_POUT ( P3OUT )
45 #define LCD_ENABLE_PIN ( BIT6 )
47 #define ENABLE_LCD_ENABLE() { \
48 LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
49 LCD_ENABLE_POUT |= LCD_ENABLE_PIN; \
52 #define DISABLE_LCD_ENABLE() { \
53 LCD_ENABLE_PDIR |= LCD_ENABLE_PIN; \
54 LCD_ENABLE_POUT &= ~LCD_ENABLE_PIN; \
57 #define LCD_CS_PDIR ( P3DIR )
58 #define LCD_CS_POUT ( P3OUT )
59 #define LCD_CS_PIN ( BIT2 )
61 #define LCD_SPI_PORT_SEL ( P3SEL )
62 #define LCD_SPI_SIMO_BIT ( BIT1 )
63 #define LCD_SPI_CLK_BIT ( BIT3 )
65 #define LCD_CS_ASSERT() { LCD_CS_POUT |= LCD_CS_PIN; }
66 #define LCD_CS_DEASSERT() { LCD_CS_POUT &= ~LCD_CS_PIN; }
68 /* unused in this version */
69 #define SPECIAL_DMA_CONFIG() { }
70 #define OLED_CS1N_ENABLE() { }
71 #define OLED_CS1N_DISABLE() { }
74 #define CONFIG_LCD_PINS() { \
75 LCD_SPI_PORT_SEL |= LCD_SPI_SIMO_BIT; \
76 LCD_SPI_PORT_SEL |= LCD_SPI_CLK_BIT; \
77 ENABLE_LCD_ENABLE(); \
78 LCD_CS_PDIR |= LCD_CS_PIN; \
82 // labeled EL_EN on schematic
83 #define LCD_LED_PDIR ( P4DIR )
84 #define LCD_LED_POUT ( P4OUT )
85 #define LCD_LED_PIN ( BIT4 )
87 #define DISABLE_LCD_LED() { \
88 LCD_LED_PDIR |= LCD_LED_PIN; \
89 LCD_LED_POUT &= ~LCD_LED_PIN; \
92 #define ENABLE_LCD_LED() { \
93 LCD_LED_PDIR |= LCD_LED_PIN; \
94 LCD_LED_POUT |= LCD_LED_PIN; \
96 // Use UCB2 as the SPI port define the registers and interrupt vector to all be
97 // for UCB2 by replacing the x in the last section of the name with a 2
98 #define LCD_SPI_UCBxCTL0 UCB0CTL0 // Control register
99 #define LCD_SPI_UCBxCTL1 UCB0CTL1 // Control register
100 #define LCD_SPI_UCBxBR0 UCB0BR0 // Baudrate prescale
101 #define LCD_SPI_UCBxBR1 UCB0BR1 // Baudrate divider
103 #define LCD_SPI_UCBxTXBUF UCB0TXBUF // Transmit buffer
104 #define LCD_SPI_UCBxRXBUF UCB0RXBUF // Receive buffer
106 #define LCD_SPI_UCBxIE UCB0IE // Interrupt enable register
107 #define LCD_SPI_UCBxIFG UCB0IFG // Interrupt flag register
108 #define LCD_SPI_UCBxIV UCB0IV // Interrupt vector register
109 #define LCD_SPI_UCBxSTAT UCB0STAT // status register
112 // Definitions for the OLED Display
113 // peripheral mapping for OLED
114 #define OLED_I2C_CTL0 ( UCB0CTL0 )
115 #define OLED_I2C_CTL1 ( UCB0CTL1 )
116 #define OLED_I2C_BR0 ( UCB0BR0 )
117 #define OLED_I2C_BR1 ( UCB0BR1 )
118 #define OLED_I2C_I2CSA ( UCB0I2CSA )
119 #define OLED_I2C_IE ( UCB0IE )
120 #define OLED_I2C_IFG ( UCB0IFG )
121 #define OLED_I2C_TXBUF ( UCB0TXBUF )
122 #define OLED_I2C_RXBUF ( UCB0RXBUF )
123 // interrupt mapping for OLED
124 #define USCI_OLED_I2C_VECTOR ( USCI_B0_VECTOR )
125 #define USCI_OLED_I2C_IV ( UCB0IV )
127 // OLED reset is active low
128 #define OLED_RSTN_PDIR ( P3DIR )
129 #define OLED_RSTN_POUT ( P3OUT )
130 #define OLED_RSTN_PIN ( BIT3 )
132 #define OLED_RSTN_CONFIG() { OLED_RSTN_PDIR |= OLED_RSTN_PIN; OLED_RSTN_ASSERT(); }
133 #define OLED_RSTN_ASSERT() { OLED_RSTN_POUT &= ~OLED_RSTN_PIN; }
134 #define OLED_RSTN_DEASSERT() { OLED_RSTN_POUT |= OLED_RSTN_PIN; }
136 #define OLED_CS1N_PDIR ( P8DIR )
137 #define OLED_CS1N_POUT ( P8OUT )
138 #define OLED_CS1N_PIN ( BIT0 )
140 #define OLED_CS1N_CONFIG() { OLED_CS1N_PDIR |= OLED_CS1N_PIN; OLED_CS1N_DISABLE(); }
141 #define OLED_CS1N_ENABLE() { OLED_CS1N_POUT &= ~OLED_CS1N_PIN; }
142 #define OLED_CS1N_DISABLE() { OLED_CS1N_POUT |= OLED_CS1N_PIN; }
144 #define OLED_CS2N_PDIR ( P8DIR )
145 #define OLED_CS2N_POUT ( P8OUT )
146 #define OLED_CS2N_PIN ( BIT1 )
148 #define OLED_CS2N_CONFIG() { OLED_CS2N_PDIR |= OLED_CS2N_PIN; OLED_CS2N_DISABLE(); }
149 #define OLED_CS2N_ENABLE() { OLED_CS2N_POUT &= ~OLED_CS2N_PIN; }
150 #define OLED_CS2N_DISABLE() { OLED_CS2N_POUT |= OLED_CS2N_PIN; }
152 #define OLED_SDA_PDIR ( P3DIR )
153 #define OLED_SDA_POUT ( P3OUT )
154 #define OLED_SDA_PIN ( BIT1 )
155 #define OLED_SDA_PSEL ( P3SEL)
157 #define OLED_SCL_PDIR ( P3DIR )
158 #define OLED_SCL_POUT ( P3OUT )
159 #define OLED_SCL_PORT ( P3 )
160 #define OLED_SCL_PIN ( BIT2 )
161 #define OLED_SCL_PSEL ( P3SEL )
163 // the select line overrides the pdir and pout settings
164 #define OLED_SDA_CONFIG_FOR_PERIPHERAL_USE() { OLED_SDA_PSEL |= OLED_SDA_PIN; }
165 #define OLED_SCL_CONFIG_FOR_PERIPHERAL_USE() { OLED_SCL_PSEL |= OLED_SCL_PIN; }
167 #define OLED_I2C_CONFIG_FOR_PERIPHERAL_USE() { \
168 OLED_SDA_CONFIG_FOR_PERIPHERAL_USE(); \
169 OLED_SCL_CONFIG_FOR_PERIPHERAL_USE(); }
171 #define OLED_SDA_CONFIG_FOR_SLEEP() { \
172 OLED_SDA_PSEL &= ~OLED_SDA_PIN; \
173 OLED_SDA_PDIR |= OLED_SDA_PIN; \
174 OLED_SDA_POUT |= OLED_SDA_PIN; }
176 #define OLED_SCL_CONFIG_FOR_SLEEP() { \
177 OLED_SCL_PSEL &= ~OLED_SCL_PIN; \
178 OLED_SCL_PDIR |= OLED_SCL_PIN; \
179 OLED_SCL_POUT |= OLED_SCL_PIN; }
181 #define OLED_I2C_CONFIG_FOR_SLEEP() { \
182 OLED_SDA_CONFIG_FOR_SLEEP(); \
183 OLED_SCL_CONFIG_FOR_SLEEP(); }
185 #define OLED_POWER_ENABLE_PIN ( BIT0 )
186 #define OLED_POWER_ENABLE_POUT ( P4OUT )
187 #define OLED_POWER_ENABLE_PDIR ( P4DIR )
188 #define OLED_POWER_CONFIG() { P4DIR |= OLED_POWER_ENABLE_PIN; OLED_POWER_DISABLE(); }
189 #define OLED_POWER_ENABLE() { P4OUT |= OLED_POWER_ENABLE_PIN; }
190 #define OLED_POWER_DISABLE() { P4OUT &= ~OLED_POWER_ENABLE_PIN; }
192 // VLED_EN is active low
193 #define OLED_IO_POWER_ENABLE_PIN ( BIT3 )
194 #define OLED_IO_POWER_ENABLE_POUT ( P5OUT )
195 #define OLED_IO_POWER_ENABLE_PDIR ( P5DIR )
196 #define OLED_IO_POWER_CONFIG() { P5DIR |= OLED_IO_POWER_ENABLE_PIN; OLED_IO_POWER_DISABLE(); }
197 #define OLED_IO_POWER_ENABLE() { P5OUT &= ~OLED_IO_POWER_ENABLE_PIN; }
198 #define OLED_IO_POWER_DISABLE() { P5OUT |= OLED_IO_POWER_ENABLE_PIN; }
207 #define CONFIG_OLED_PINS() { }
210 // Real time clock defines
211 // RTC 1 Hz output, also used to toggle the bias on the LCD
212 #define RTC_1HZ_PORT_DIR ( P2DIR )
213 #define RTC_1HZ_PORT_SEL ( P2SEL )
214 #define RTC_1HZ_BIT ( BIT4 )
219 #define BUTTON_TIME_COUNT_ARRAY_LEN 8
220 #define ALL_BUTTONS_OFF 0xFF
231 #define SW_A_INDEX ( 0 )
232 #define SW_B_INDEX ( 1 )
233 #define SW_C_INDEX ( 2 )
234 #define SW_D_INDEX ( 3 )
235 #define SW_UNUSED_INDEX ( 4 )
236 #define SW_E_INDEX ( 5 )
237 #define SW_F_INDEX ( 6 )
238 #define SW_P_INDEX ( 7 )
239 /* the switch does not count */
240 #define TOTAL_BTN_NUM ( 7 )
243 #define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_D | SW_E | SW_F | SW_P)
244 #elif defined(DIGITAL)
245 #define ALL_BUTTONS (SW_A | SW_B | SW_C | SW_D | SW_E | SW_F)
248 // The digital watch version 1 has 1 Meg pull downs
249 // so the code below wont work
250 #define RESISTOR_ENABLE_BUTTONS ALL_BUTTONS
252 // Setting the edge select bit high generates and interrupt on the falling edge
253 #define INT_EDGE_SEL_BUTTONS (ALL_BUTTONS)
255 #define BUTTON_PORT_VECTOR PORT2_VECTOR
256 #define BUTTON_PORT_DIR P2DIR
257 #define BUTTON_PORT_SEL P2SEL
258 #define BUTTON_PORT_OUT P2OUT
259 #define BUTTON_PORT_REN P2REN
260 #define BUTTON_PORT_IE P2IE
261 #define BUTTON_PORT_IES P2IES
262 #define BUTTON_PORT_IFG P2IFG
264 #define DISABLE_BUTTONS() { \
265 BUTTON_PORT_IE &= ~INT_EDGE_SEL_BUTTONS; \
266 BUTTON_PORT_REN &= ~ALL_BUTTONS; \
267 BUTTON_PORT_OUT &= ~ALL_BUTTONS; \
271 /* S5 or SW_E is the button that takes the watch out of shipping mode */
272 #define ENABLE_SHIPPING_WAKEUP() { \
276 RTCPS0CTL = 0x0000; \
277 RTCPS1CTL = 0x0000; \
279 BUTTON_PORT_REN = SW_E; \
280 BUTTON_PORT_OUT = SW_E; \
281 BUTTON_PORT_DIR &= ~SW_E; \
282 BUTTON_PORT_IES |= SW_E; \
283 BUTTON_PORT_IFG = 0x00; \
284 BUTTON_PORT_IE |= SW_E; \
287 // NOTE the the buttons are grounded. That means that we want to invert the bits
288 // when reading the port to have positive logic where a button press is a "1"
289 #define BUTTON_PORT_IN ~P2IN
291 // Configure the hardware port for the button support P2.4 is excluded
292 #define CONFIGURE_BUTTON_PINS() { \
293 BUTTON_PORT_REN = (unsigned char) RESISTOR_ENABLE_BUTTONS; \
294 BUTTON_PORT_OUT = (unsigned char) ALL_BUTTONS; \
295 BUTTON_PORT_DIR &= (unsigned char) ~ALL_BUTTONS; \
296 BUTTON_PORT_IES |= INT_EDGE_SEL_BUTTONS; \
297 BUTTON_PORT_IFG &= ~ALL_BUTTONS; \
298 BUTTON_PORT_IE |= ALL_BUTTONS; \
302 // Battery charger control for a BQ24080
303 #define BAT_CHARGE_DIR P6DIR
304 #define BAT_CHARGE_REN P6REN
305 #define BAT_CHARGE_OUT P6OUT
306 #define BAT_CHARGE_IN P6IN
308 #define BAT_CHARGE_ENABLE_PIN BIT2
309 #define BAT_CHARGE_STAT1 BIT3
310 #define BAT_CHARGE_STAT2 BIT4
311 #define BAT_CHARGE_PWR_BIT BIT5
313 // Enable charging, asserted low
314 #define BATTERY_CHARGE_ENABLE() { BAT_CHARGE_OUT &= ~BAT_CHARGE_ENABLE_PIN; }
316 // disable charging, sleep the part
317 #define BATTERY_CHARGE_DISABLE() { BAT_CHARGE_OUT |= BAT_CHARGE_ENABLE_PIN; }
321 // Ambient Light Sensor
323 #define GC1_PDIR ( P6DIR )
324 #define GC1_POUT ( P6OUT )
325 #define GC1_PSEL ( P6SEL )
326 #define GC1_PIN ( BIT0 )
328 #define GC2_PDIR ( P6DIR )
329 #define GC2_POUT ( P6OUT )
330 #define GC2_PSEL ( P6SEL )
331 #define GC2_PIN ( BIT6 )
333 #define IOUT_PDIR ( P6DIR )
334 #define IOUT_PSEL ( P6SEL )
335 #define IOUT_PIN ( BIT1 )
337 #define LIGHT_SENSE_INIT() \
339 IOUT_PDIR &= ~IOUT_PIN; \
340 IOUT_PSEL |= IOUT_PIN; \
341 GC1_PDIR |= GC1_PIN; \
342 GC2_PDIR |= GC2_PIN; \
343 LIGHT_SENSE_DISABLE(); \
346 #define LIGHT_SENSOR_SHUTDOWN() \
348 GC1_POUT &= ~GC1_PIN; \
349 GC2_POUT &= ~GC2_PIN; \
352 #define LIGHT_SENSOR_L_GAIN() \
354 GC1_POUT |= GC1_PIN; \
355 GC2_POUT |= GC2_PIN; \
358 #define LIGHT_SENSE_ENABLE()\
360 LIGHT_SENSOR_L_GAIN(); \
363 #define LIGHT_SENSE_DISABLE() \
365 LIGHT_SENSOR_SHUTDOWN(); \
371 // This pin controls if the battery voltage can be read
373 #define BATTERY_READ_CONTROL_PDIR ( P4DIR )
374 #define BATTERY_READ_CONTROL_POUT ( P4OUT )
375 #define BATTERY_READ_CONTROL_PIN ( BIT6 )
377 #define BATTERY_SENSE_INPUT_PDIR ( P7DIR )
378 #define BATTERY_SENSE_INPUT_PSEL ( P7SEL )
379 #define BATTERY_SENSE_INPUT_PIN ( BIT7 )
381 #define BATTERY_SENSE_INIT() \
383 BATTERY_READ_CONTROL_PDIR |= BATTERY_READ_CONTROL_PIN; \
384 BATTERY_SENSE_INPUT_PDIR &= ~BATTERY_SENSE_INPUT_PIN; \
385 BATTERY_SENSE_INPUT_PSEL |= BATTERY_SENSE_INPUT_PIN; \
386 BATTERY_SENSE_DISABLE(); \
389 #define BATTERY_SENSE_ENABLE() \
391 BATTERY_READ_CONTROL_POUT |= BATTERY_READ_CONTROL_PIN; \
394 #define BATTERY_SENSE_DISABLE() \
396 BATTERY_READ_CONTROL_POUT &= ~BATTERY_READ_CONTROL_PIN; \
400 // hardware configuration is a voltage divider to ADC input
402 #define HARDWARE_CFG_CONTROL_PDIR ( P8DIR )
403 #define HARDWARE_CFG_CONTROL_POUT ( P8OUT )
404 #define HARDWARE_CFG_CONTROL_PIN ( BIT2 )
406 #define HARDWARE_CFG_INPUT_PDIR ( P7DIR )
407 #define HARDWARE_CFG_INPUT_PSEL ( P7SEL )
408 #define HARDWARE_CFG_INPUT_PIN ( BIT5 )
410 #define HARDWARE_CFG_SENSE_INIT() \
412 HARDWARE_CFG_CONTROL_PDIR |= HARDWARE_CFG_CONTROL_PIN; \
413 HARDWARE_CFG_INPUT_PDIR &= ~HARDWARE_CFG_INPUT_PIN; \
414 HARDWARE_CFG_INPUT_PSEL |= HARDWARE_CFG_INPUT_PIN; \
415 HARDWARE_CFG_SENSE_DISABLE(); \
418 #define HARDWARE_CFG_SENSE_ENABLE() \
420 HARDWARE_CFG_CONTROL_POUT |= HARDWARE_CFG_CONTROL_PIN; \
423 #define HARDWARE_CFG_SENSE_DISABLE() \
425 HARDWARE_CFG_CONTROL_POUT &= ~HARDWARE_CFG_CONTROL_PIN; \
429 #define APPLE_SDA_PDIR ( P10DIR )
430 #define APPLE_SDA_POUT ( P10OUT )
431 #define APPLE_SDA_PIN ( BIT1 )
433 #define APPLE_SCL_PDIR ( P10DIR )
434 #define APPLE_SCL_POUT ( P10OUT )
435 #define APPLE_SCL_PIN ( BIT2 )
437 #define APPLE_POWER_PDIR ( P4DIR )
438 #define APPLE_POWER_POUT ( P4OUT )
439 #define APPLE_POWER_PIN ( BIT5 )
441 /* power enable is active low */
442 #define APPLE_POWER_ENABLE() { APPLE_POWER_POUT &= ~APPLE_POWER_PIN; }
443 #define APPLE_POWER_DISABLE() { APPLE_POWER_POUT |= APPLE_POWER_PIN; }
445 #define APPLE_POWER_CONFIG() { \
446 APPLE_POWER_PDIR |= APPLE_POWER_PIN; \
447 APPLE_POWER_DISABLE(); \
451 /* since the apple chip is currently not powered
452 * the pins should be at 0 instead of 1
454 #define APPLE_I2C_PIN_CONFIG() { \
455 APPLE_SDA_PDIR |= APPLE_SDA_PIN; \
456 APPLE_SDA_POUT &= ~APPLE_SDA_PIN; \
457 APPLE_SCL_PDIR |= APPLE_SCL_PIN; \
458 APPLE_SCL_POUT &= ~APPLE_SCL_PIN; \
461 #define APPLE_CONFIG() { \
462 APPLE_POWER_CONFIG(); \
463 APPLE_I2C_PIN_CONFIG(); \
466 #define SRAM_SCLK_PSEL ( P3SEL )
467 #define SRAM_SCLK_PDIR ( P3DIR )
468 #define SRAM_SCLK_POUT ( P3OUT )
469 #define SRAM_SCLK_PIN ( BIT0 )
471 #define SRAM_SOMI_PSEL ( P3SEL )
472 #define SRAM_SOMI_PDIR ( P3DIR )
473 #define SRAM_SOMI_POUT ( P3OUT )
474 #define SRAM_SOMI_PIN ( BIT5 )
476 #define SRAM_SIMO_PSEL ( P3SEL )
477 #define SRAM_SIMO_PDIR ( P3DIR )
478 #define SRAM_SIMO_POUT ( P3OUT )
479 #define SRAM_SIMO_PIN ( BIT4 )
481 #define SRAM_CSN_PDIR ( P9DIR )
482 #define SRAM_CSN_POUT ( P9OUT )
483 #define SRAM_CSN_PIN ( BIT6)
485 #define SRAM_HOLDN_PDIR ( P9DIR )
486 #define SRAM_HOLDN_POUT ( P9OUT )
487 #define SRAM_HOLDN_PIN ( BIT7 )
489 #define CONFIG_SRAM_PINS() \
491 SRAM_CSN_PDIR |= SRAM_CSN_PIN; \
492 SRAM_CSN_POUT |= SRAM_CSN_PIN; \
493 SRAM_HOLDN_PDIR |= SRAM_HOLDN_PIN; \
494 SRAM_HOLDN_POUT |= SRAM_HOLDN_PIN; \
497 #define SRAM_CSN_ASSERT() { SRAM_CSN_POUT &= ~SRAM_CSN_PIN; }
499 #define SRAM_CSN_DEASSERT() { \
500 WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE(); \
501 SRAM_CSN_POUT |= SRAM_CSN_PIN; \
504 /* wait for shift to complete ( ~3 us ) */
505 #define WAIT_FOR_SRAM_SPI_SHIFT_COMPLETE() { while( (UCA0STAT & 0x01) != 0 ); }
507 #define ACCELEROMETER_SDA_PIN ( BIT7 )
508 #define ACCELEROMETER_SDA_PSEL ( P3SEL )
509 #define ACCELEROMETER_SDA_POUT ( P3OUT )
510 #define ACCELEROMETER_SDA_PDIR ( P3OUT )
511 #define ACCELEROMETER_SDA_PREN ( P1REN )
513 #define ACCELEROMETER_SCL_PIN ( BIT4 )
514 #define ACCELEROMETER_SCL_PSEL ( P5SEL )
515 #define ACCELEROMETER_SCL_POUT ( P5OUT )
516 #define ACCELEROMETER_SCL_PDIR ( P5OUT )
517 #define ACCELEROMETER_SCL_PREN ( P5REN )
519 #define ACCELEROMETER_INT_PIN ( BIT7 )
520 #define ACCELEROMETER_INT_PDIR ( P1DIR )
521 #define ACCELEROMETER_INT_PSEL ( P1SEL )
522 #define ACCELEROMETER_INT_PIFG ( P1IFG )
523 #define ACCELEROMETER_INT_PIE ( P1IE )
525 #define ACCELEROMETER_POWER_POUT ( P9OUT )
526 #define ACCELEROMETER_POWER_PDIR ( P9DIR )
527 #define ACCELEROMETER_POWER_PINS ( BIT1 | BIT2 )
529 /* this is for reference only (it doesn't control anything) */
530 #define ACCELEROMETER_INT_NUM (PIN7_INT)
532 #define LED4_ON() { }
533 #define LED5_ON() { }
534 #define LED6_ON() { }
535 #define LED7_ON() { }
537 #define LED4_OFF() { }
538 #define LED5_OFF() { }
539 #define LED6_OFF() { }
540 #define LED7_OFF() { }
542 #define CONFIG_LED_PINS() { }
546 #define DEBUG1_HIGH() { }
547 #define DEBUG3_HIGH() { }
548 #define DEBUG4_HIGH() { }
549 #define DEBUG5_HIGH() { }
551 #define DEBUG1_LOW() { }
552 #define DEBUG3_LOW() { }
553 #define DEBUG4_LOW() { }
554 #define DEBUG5_LOW() { }
556 #define DEBUG1_PULSE() { }
557 #define DEBUG3_PULSE() { }
558 #define DEBUG4_PULSE() { }
559 #define DEBUG5_PULSE() { }
561 #define DEBUG1_TOGGLE() { }
562 #define DEBUG3_TOGGLE() { }
563 #define DEBUG4_TOGGLE() { }
564 #define DEBUG5_TOGGLE() { }
566 #define CONFIG_DEBUG_PINS() { }
569 * Sideband signals (for lack of another word)
571 #define BT_CLK_REQ_PDIR ( P1DIR )
572 #define BT_CLK_REQ_POUT ( P1OUT )
573 #define BT_CLK_REQ_PIN ( BIT4 )
575 #define BT_IO1_PDIR ( P1DIR )
576 #define BT_IO1_POUT ( P1OUT )
577 #define BT_IO1_PIN ( BIT5 )
579 #define BT_IO2_PDIR ( P1DIR )
580 #define BT_IO2_POUT ( P1OUT )
581 #define BT_IO2_PIN ( BIT6 )
583 /******************************************************************************/
585 /* peripheral mapping for accelerometer */
586 #define ACCELEROMETER_CTL0 ( UCB1CTL0 )
587 #define ACCELEROMETER_CTL1 ( UCB1CTL1 )
588 #define ACCELEROMETER_BR0 ( UCB1BR0 )
589 #define ACCELEROMETER_BR1 ( UCB1BR1 )
590 #define ACCELEROMETER_I2CSA ( UCB1I2CSA )
591 #define ACCELEROMETER_IE ( UCB1IE )
592 #define ACCELEROMETER_IFG ( UCB1IFG )
593 #define ACCELEROMETER_TXBUF ( UCB1TXBUF )
594 #define ACCELEROMETER_RXBUF ( UCB1RXBUF )
595 #define ACCELEROMETER_STAT ( UCB1STAT )
596 /* interrupt mapping for accelerometer */
597 #define USCI_ACCELEROMETER_VECTOR ( USCI_B1_VECTOR )
598 #define USCI_ACCELEROMETER_IV ( UCB1IV )
600 /******************************************************************************/
603 #define MUX_CONTROL1_PDIR ( P10DIR )
604 #define MUX_CONTROL1_POUT ( P10OUT )
605 #define MUX_CONTROL1_PIN ( BIT7 )
607 #define MUX_CONTROL2_PDIR ( P10DIR )
608 #define MUX_CONTROL2_POUT ( P10OUT )
609 #define MUX_CONTROL2_PIN ( BIT6 )
612 #endif // HAL_DIGITAL_V2_DEFS_H