arch/arm/boot/dts/imx6sx-sdb.dts

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/input/input.h>
  12 #include "imx6sx.dtsi"
  13
  14 / {
  15         model = "Freescale i.MX6 SoloX SDB Board";
  16         compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
  17
  18         chosen {
  19                 stdout-path = &uart1;
  20         };
  21
  22         memory {
  23                 reg = <0x80000000 0x40000000>;
  24         };
  25
  26         backlight1 {
  27                 compatible = "pwm-backlight";
  28                 pwms = <&pwm3 0 5000000>;
  29                 brightness-levels = <0 4 8 16 32 64 128 255>;
  30                 default-brightness-level = <6>;
  31                 fb-names = "mxs-lcdif0";
  32         };
  33
  34         backlight2 {
  35                 compatible = "pwm-backlight";
  36                 pwms = <&pwm4 0 5000000>;
  37                 brightness-levels = <0 4 8 16 32 64 128 255>;
  38                 default-brightness-level = <6>;
  39                 fb-names = "mxs-lcdif1";
  40         };
  41
  42         gpio-keys {
  43                 compatible = "gpio-keys";
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_gpio_keys>;
  46
  47                 volume-up {
  48                         label = "Volume Up";
  49                         gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
  50                         linux,code = <KEY_VOLUMEUP>;
  51                 };
  52
  53                 volume-down {
  54                         label = "Volume Down";
  55                         gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  56                         linux,code = <KEY_VOLUMEDOWN>;
  57                 };
  58         };
  59
  60         hannstar_cabc {
  61                 compatible = "hannstar,cabc";
  62
  63                 lvds0 {
  64                         gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
  65                 };
  66         };
  67
  68         pxp_v4l2_out {
  69                 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
  70                 status = "okay";
  71         };
  72
  73         regulators {
  74                 compatible = "simple-bus";
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77
  78                 reg_lcd_3v3: lcd-3v3 {
  79                         compatible = "regulator-fixed";
  80                         regulator-name = "lcd-3v3";
  81                         gpio = <&gpio3 27 0>;
  82                         enable-active-high;
  83                         status = "disabled";
  84                 };
  85
  86                 vcc_sd3: regulator@0 {
  87                         compatible = "regulator-fixed";
  88                         reg = <0>;
  89                         pinctrl-names = "default";
  90                         pinctrl-0 = <&pinctrl_vcc_sd3>;
  91                         regulator-name = "VCC_SD3";
  92                         regulator-min-microvolt = <3000000>;
  93                         regulator-max-microvolt = <3000000>;
  94                         gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  95                         enable-active-high;
  96                 };
  97
  98                 reg_psu_5v: regulator@1 {
  99                         compatible = "regulator-fixed";
 100                         reg = <1>;
 101                         regulator-name = "PSU-5V0";
 102                         regulator-min-microvolt = <5000000>;
 103                         regulator-max-microvolt = <5000000>;
 104                         regulator-boot-on;
 105                 };
 106
 107                 reg_vref_3v3: regulator@2 {
 108                         compatible = "regulator-fixed";
 109                         regulator-name = "vref-3v3";
 110                         regulator-min-microvolt = <3300000>;
 111                         regulator-max-microvolt = <3300000>;
 112                 };
 113
 114                 reg_usb_otg1_vbus: regulator@3 {
 115                         compatible = "regulator-fixed";
 116                         reg = <3>;
 117                         pinctrl-names = "default";
 118                         pinctrl-0 = <&pinctrl_usb_otg1>;
 119                         regulator-name = "usb_otg1_vbus";
 120                         regulator-min-microvolt = <5000000>;
 121                         regulator-max-microvolt = <5000000>;
 122                         gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 123                         enable-active-high;
 124                 };
 125
 126                 reg_usb_otg2_vbus: regulator@4 {
 127                         compatible = "regulator-fixed";
 128                         reg = <4>;
 129                         pinctrl-names = "default";
 130                         pinctrl-0 = <&pinctrl_usb_otg2>;
 131                         regulator-name = "usb_otg2_vbus";
 132                         regulator-min-microvolt = <5000000>;
 133                         regulator-max-microvolt = <5000000>;
 134                         gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 135                         enable-active-high;
 136                 };
 137
 138                 reg_pcie: regulator@5 {
 139                         compatible = "regulator-fixed";
 140                         reg = <5>;
 141                         pinctrl-names = "default";
 142                         pinctrl-0 = <&pinctrl_pcie_reg>;
 143                         regulator-name = "MPCIE_3V3";
 144                         regulator-min-microvolt = <3300000>;
 145                         regulator-max-microvolt = <3300000>;
 146                         gpio = <&gpio2 1 0>;
 147                         regulator-always-on;
 148                         enable-active-high;
 149                 };
 150         };
 151
 152         sound {
 153                 compatible = "fsl,imx6q-sabresd-wm8962",
 154                            "fsl,imx-audio-wm8962";
 155                 model = "wm8962-audio";
 156                 cpu-dai = <&ssi2>;
 157                 audio-codec = <&codec>;
 158                 audio-routing =
 159                         "Headphone Jack", "HPOUTL",
 160                         "Headphone Jack", "HPOUTR",
 161                         "Ext Spk", "SPKOUTL",
 162                         "Ext Spk", "SPKOUTR",
 163                         "AMIC", "MICBIAS",
 164                         "IN3R", "AMIC";
 165                 mux-int-port = <2>;
 166                 mux-ext-port = <6>;
 167                 hp-det-gpios = <&gpio1 17 1>;
 168         };
 169
 170         sound-spdif {
 171                 compatible = "fsl,imx-audio-spdif",
 172                            "fsl,imx6sx-sdb-spdif";
 173                 model = "imx-spdif";
 174                 spdif-controller = <&spdif>;
 175                 spdif-out;
 176         };
 177
 178         sii902x_reset: sii902x-reset {
 179                 compatible = "gpio-reset";
 180                 reset-gpios = <&gpio3 27 1>;
 181                 reset-delay-us = <100000>;
 182                 #reset-cells = <0>;
 183         };
 184 };
 185
 186 &adc1 {
 187         vref-supply = <&reg_vref_3v3>;
 188         status = "okay";
 189 };
 190
 191 &adc2 {
 192         vref-supply = <&reg_vref_3v3>;
 193         status = "okay";
 194 };
 195
 196 &audmux {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_audmux>;
 199         status = "okay";
 200 };
 201
 202 &csi1 {
 203         status = "okay";
 204
 205         port {
 206                 csi1_ep: endpoint {
 207                         remote-endpoint = <&ov5640_ep>;
 208                 };
 209         };
 210 };
 211
 212 &csi2 {
 213         status = "okay";
 214         port {
 215                 csi2_ep: endpoint {
 216                         remote-endpoint = <&vadc_ep>;
 217                 };
 218         };
 219 };
 220
 221 &cpu0 {
 222         operating-points = <
 223                 /* kHz    uV */
 224                 996000  1250000
 225                 792000  1175000
 226                 396000  1175000
 227                 198000  1175000
 228                 >;
 229         fsl,soc-operating-points = <
 230                 /* ARM kHz      SOC uV */
 231                 996000  1250000
 232                 792000  1175000
 233                 396000  1175000
 234                 198000  1175000
 235         >;
 236         arm-supply = <&sw1a_reg>;
 237         soc-supply = <&sw1a_reg>;
 238         fsl,arm-soc-shared = <1>;
 239 };
 240
 241 &gpc {
 242         /* use ldo-bypass, u-boot will check it and configure */
 243         fsl,ldo-bypass = <1>;
 244 };
 245
 246 &lcdif1 {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_lcdif_dat
 249                      &pinctrl_lcdif_ctrl>;
 250         lcd-supply = <&reg_lcd_3v3>;
 251         display = <&display0>;
 252         status = "disabled";
 253
 254         display0: display {
 255                 bits-per-pixel = <16>;
 256                 bus-width = <24>;
 257
 258                 display-timings {
 259                         native-mode = <&timing0>;
 260                         timing0: timing0 {
 261                                 clock-frequency = <33500000>;
 262                                 hactive = <800>;
 263                                 vactive = <480>;
 264                                 hback-porch = <89>;
 265                                 hfront-porch = <164>;
 266                                 vback-porch = <23>;
 267                                 vfront-porch = <10>;
 268                                 hsync-len = <10>;
 269                                 vsync-len = <10>;
 270                                 hsync-active = <0>;
 271                                 vsync-active = <0>;
 272                                 de-active = <1>;
 273                                 pixelclk-active = <0>;
 274                         };
 275                 };
 276         };
 277 };
 278
 279 &lcdif2 {
 280         display = <&display1>;
 281         disp-dev = "ldb";
 282         status = "okay";
 283
 284         display1: display {
 285                 bits-per-pixel = <16>;
 286                 bus-width = <18>;
 287         };
 288 };
 289
 290 &ldb {
 291         status = "okay";
 292
 293         lvds-channel@0 {
 294                 fsl,data-mapping = "spwg";
 295                 fsl,data-width = <18>;
 296                 crtc = "lcdif2";
 297                 status = "okay";
 298
 299                 display-timings {
 300                         native-mode = <&timing1>;
 301                         timing1: hsd100pxn1 {
 302                                 clock-frequency = <65000000>;
 303                                 hactive = <1024>;
 304                                 vactive = <768>;
 305                                 hback-porch = <220>;
 306                                 hfront-porch = <40>;
 307                                 vback-porch = <21>;
 308                                 vfront-porch = <7>;
 309                                 hsync-len = <60>;
 310                                 vsync-len = <10>;
 311                         };
 312                 };
 313         };
 314 };
 315
 316 &pwm3 {
 317         pinctrl-names = "default";
 318         pinctrl-0 = <&pinctrl_pwm3>;
 319         status = "okay";
 320 };
 321
 322 &pwm4 {
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_pwm4>;
 325         status = "okay";
 326 };
 327
 328 &dcic1 {
 329         dcic_id = <0>;
 330         dcic_mux = "dcic-lcdif1";
 331         status = "okay";
 332 };
 333
 334 &dcic2 {
 335         dcic_id = <1>;
 336         dcic_mux = "dcic-lvds";
 337         status = "okay";
 338 };
 339
 340 &fec1 {
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pinctrl_enet1>;
 343         pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6 GPIO_ACTIVE_LOW>;
 344         phy-mode = "rgmii";
 345         status = "okay";
 346 };
 347
 348 &fec2 {
 349         pinctrl-names = "default";
 350         pinctrl-0 = <&pinctrl_enet2>;
 351         phy-mode = "rgmii";
 352         status = "okay";
 353 };
 354
 355 &flexcan1 {
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&pinctrl_flexcan1>;
 358         trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_LOW>;
 359         trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
 360         status = "okay";
 361 };
 362
 363 &flexcan2 {
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_flexcan2>;
 366         trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_LOW>;
 367         trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
 368         status = "okay";
 369 };
 370
 371 &pcie {
 372         pinctrl-names = "default";
 373         pinctrl-0 = <&pinctrl_pcie>;
 374         reset-gpio = <&gpio2 0 0>;
 375         status = "okay";
 376 };
 377
 378 &qspi2 {
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_qspi2_1>;
 381         status = "okay";
 382
 383 #ifndef SPANSIONFLASH
 384         ddrsmp=<0>;
 385
 386         flash0: n25q256a@0 {
 387                 #address-cells = <1>;
 388                 #size-cells = <1>;
 389                 compatible = "micron,n25q256a";
 390                 spi-max-frequency = <29000000>;
 391                 spi-nor,ddr-quad-read-dummy = <6>;
 392                 reg = <0>;
 393         };
 394
 395         flash1: n25q256a@1 {
 396                 #address-cells = <1>;
 397                 #size-cells = <1>;
 398                 compatible = "micron,n25q256a";
 399                 spi-max-frequency = <29000000>;
 400                 spi-nor,ddr-quad-read-dummy = <6>;
 401                 reg = <1>;
 402         };
 403 #endif
 404 };
 405
 406 &pxp {
 407         status = "okay";
 408 };
 409
 410 &sai1 {
 411         pinctrl-names = "default";
 412         pinctrl-0 = <&pinctrl_sai1>;
 413         status = "disabled";
 414 };
 415
 416 &spdif {
 417         pinctrl-names = "default";
 418         pinctrl-0 = <&pinctrl_spdif>;
 419         status = "okay";
 420 };
 421
 422 &ssi2 {
 423         status = "okay";
 424 };
 425
 426 &uart1 {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_uart1>;
 429         status = "okay";
 430 };
 431
 432 &uart5 { /* for bluetooth */
 433         pinctrl-names = "default";
 434         pinctrl-0 = <&pinctrl_uart5>;
 435         fsl,uart-has-rtscts;
 436         status = "okay";
 437         /* for DTE mode, add below change */
 438         /* fsl,dte-mode;*/
 439         /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
 440 };
 441
 442 &usbotg1 {
 443         vbus-supply = <&reg_usb_otg1_vbus>;
 444         pinctrl-names = "default";
 445         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 446         status = "okay";
 447 };
 448
 449 &usbotg2 {
 450         vbus-supply = <&reg_usb_otg2_vbus>;
 451         dr_mode = "host";
 452         status = "okay";
 453 };
 454
 455 &usdhc2 {
 456         pinctrl-names = "default";
 457         pinctrl-0 = <&pinctrl_usdhc2>;
 458         non-removable;
 459         no-1-8-v;
 460         keep-power-in-suspend;
 461         enable-sdio-wakeup;
 462         status = "okay";
 463 };
 464
 465 &usdhc3 {
 466         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 467         pinctrl-0 = <&pinctrl_usdhc3>;
 468         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 469         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 470         bus-width = <8>;
 471         cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
 472         wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 473         keep-power-in-suspend;
 474         enable-sdio-wakeup;
 475         vmmc-supply = <&vcc_sd3>;
 476         status = "okay";
 477 };
 478
 479 &usdhc4 {
 480         pinctrl-names = "default";
 481         pinctrl-0 = <&pinctrl_usdhc4>;
 482         cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
 483         wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
 484         status = "okay";
 485 };
 486
 487 &i2c1 {
 488         clock-frequency = <100000>;
 489         pinctrl-names = "default";
 490         pinctrl-0 = <&pinctrl_i2c1>;
 491         status = "okay";
 492
 493         pmic: pfuze100@08 {
 494                 compatible = "fsl,pfuze200";
 495                 reg = <0x08>;
 496
 497                 regulators {
 498                         sw1a_reg: sw1ab {
 499                                 regulator-min-microvolt = <300000>;
 500                                 regulator-max-microvolt = <1875000>;
 501                                 regulator-boot-on;
 502                                 regulator-always-on;
 503                                 regulator-ramp-delay = <6250>;
 504                         };
 505
 506                         sw2_reg: sw2 {
 507                                 regulator-min-microvolt = <800000>;
 508                                 regulator-max-microvolt = <3300000>;
 509                                 regulator-boot-on;
 510                                 regulator-always-on;
 511                         };
 512
 513                         sw3a_reg: sw3a {
 514                                 regulator-min-microvolt = <400000>;
 515                                 regulator-max-microvolt = <1975000>;
 516                                 regulator-boot-on;
 517                                 regulator-always-on;
 518                         };
 519
 520                         sw3b_reg: sw3b {
 521                                 regulator-min-microvolt = <400000>;
 522                                 regulator-max-microvolt = <1975000>;
 523                                 regulator-boot-on;
 524                                 regulator-always-on;
 525                         };
 526
 527                         swbst_reg: swbst {
 528                                 regulator-min-microvolt = <5000000>;
 529                                 regulator-max-microvolt = <5150000>;
 530                         };
 531
 532                         snvs_reg: vsnvs {
 533                                 regulator-min-microvolt = <1000000>;
 534                                 regulator-max-microvolt = <3000000>;
 535                                 regulator-boot-on;
 536                                 regulator-always-on;
 537                         };
 538
 539                         vref_reg: vrefddr {
 540                                 regulator-boot-on;
 541                                 regulator-always-on;
 542                         };
 543
 544                         vgen1_reg: vgen1 {
 545                                 regulator-min-microvolt = <800000>;
 546                                 regulator-max-microvolt = <1550000>;
 547                                 regulator-always-on;
 548                         };
 549
 550                         vgen2_reg: vgen2 {
 551                                 regulator-min-microvolt = <800000>;
 552                                 regulator-max-microvolt = <1550000>;
 553                         };
 554
 555                         vgen3_reg: vgen3 {
 556                                 regulator-min-microvolt = <1800000>;
 557                                 regulator-max-microvolt = <3300000>;
 558                                 regulator-always-on;
 559                         };
 560
 561                         vgen4_reg: vgen4 {
 562                                 regulator-min-microvolt = <1800000>;
 563                                 regulator-max-microvolt = <3300000>;
 564                                 regulator-always-on;
 565                         };
 566
 567                         vgen5_reg: vgen5 {
 568                                 regulator-min-microvolt = <1800000>;
 569                                 regulator-max-microvolt = <3300000>;
 570                                 regulator-always-on;
 571                         };
 572
 573                         vgen6_reg: vgen6 {
 574                                 regulator-min-microvolt = <1800000>;
 575                                 regulator-max-microvolt = <3300000>;
 576                                 regulator-always-on;
 577                         };
 578                 };
 579         };
 580
 581         ov5640: ov5640@3c {
 582                 compatible = "ovti,ov5640";
 583                 reg = <0x3c>;
 584                 pinctrl-names = "default";
 585                 pinctrl-0 = <&pinctrl_csi_0>;
 586                 clocks = <&clks IMX6SX_CLK_CSI>;
 587                 clock-names = "csi_mclk";
 588                 AVDD-supply = <&vgen3_reg>;  /* 2.8v */
 589                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 590                 pwn-gpios = <&gpio3 28 1>;
 591                 rst-gpios = <&gpio3 27 0>;
 592                 csi_id = <0>;
 593                 mclk = <24000000>;
 594                 mclk_source = <0>;
 595                 port {
 596                         ov5640_ep: endpoint {
 597                                 remote-endpoint = <&csi1_ep>;
 598                         };
 599                 };
 600         };
 601
 602         sii902x@39 {
 603                 compatible = "SiI,sii902x";
 604                 interrupt-parent = <&gpio4>;
 605                 interrupts = <21 2>;
 606                 mode_str ="1280x720M@60";
 607                 bits-per-pixel = <32>;
 608                 resets = <&sii902x_reset>;
 609                 reg = <0x39>;
 610         };
 611 };
 612
 613 &i2c2 {
 614         clock-frequency = <100000>;
 615         pinctrl-names = "default";
 616         pinctrl-0 = <&pinctrl_i2c2>;
 617         status = "okay";
 618
 619         egalax_ts@04 {
 620                 compatible = "eeti,egalax_ts";
 621                 reg = <0x04>;
 622                 pinctrl-names = "default";
 623                 pinctrl-0 = <&pinctrl_egalax_int>;
 624                 interrupt-parent = <&gpio4>;
 625                 interrupts = <19 2>;
 626                 wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
 627         };
 628 };
 629
 630 &i2c3 {
 631         clock-frequency = <100000>;
 632         pinctrl-names = "default";
 633         pinctrl-0 = <&pinctrl_i2c3>;
 634         status = "okay";
 635
 636         mma8451@1c {
 637                 compatible = "fsl,mma8451";
 638                 reg = <0x1c>;
 639                 position = <1>;
 640                 interrupt-parent = <&gpio6>;
 641                 interrupts = <2 8>;
 642                 interrupt-route = <2>;
 643         };
 644
 645         mag3110@0e {
 646                 compatible = "fsl,mag3110";
 647                 reg = <0x0e>;
 648                 position = <2>;
 649                 interrupt-parent = <&gpio6>;
 650                 interrupts = <5 1>;
 651                 shared-interrupt;
 652         };
 653
 654         isl29023@44 {
 655                 compatible = "fsl,isl29023";
 656                 reg = <0x44>;
 657                 rext = <499>;
 658                 interrupt-parent = <&gpio6>;
 659                 interrupts = <5 1>;
 660                 shared-interrupt;
 661         };
 662 };
 663
 664 &i2c4 {
 665         clock-frequency = <100000>;
 666         pinctrl-names = "default";
 667         pinctrl-0 = <&pinctrl_i2c4>;
 668         status = "okay";
 669
 670         codec: wm8962@1a {
 671                 compatible = "wlf,wm8962";
 672                 reg = <0x1a>;
 673                 clocks = <&clks IMX6SX_CLK_AUDIO>;
 674                 DCVDD-supply = <&vgen4_reg>;
 675                 DBVDD-supply = <&vgen4_reg>;
 676                 AVDD-supply = <&vgen4_reg>;
 677                 CPVDD-supply = <&vgen4_reg>;
 678                 MICVDD-supply = <&vgen3_reg>;
 679                 PLLVDD-supply = <&vgen4_reg>;
 680                 SPKVDD1-supply = <&reg_psu_5v>;
 681                 SPKVDD2-supply = <&reg_psu_5v>;
 682                 amic-mono;
 683         };
 684 };
 685
 686 &vadc {
 687         vadc_in = <0>;
 688         csi_id = <1>;
 689         status = "okay";
 690         port {
 691                 vadc_ep: endpoint {
 692                         remote-endpoint = <&csi2_ep>;
 693                 };
 694         };
 695 };
 696
 697 &iomuxc {
 698         pinctrl-names = "default";
 699         pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>;
 700
 701         imx6x-sdb {
 702                 pinctrl_hog: hoggrp {
 703                         fsl,pins = <
 704                                 MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
 705                                 MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
 706                                 MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
 707                                 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
 708                                 MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21  0x17059
 709                         >;
 710                 };
 711
 712                 pinctrl_audmux: audmuxgrp {
 713                         fsl,pins = <
 714                                 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
 715                                 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
 716                                 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
 717                                 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
 718                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
 719                         >;
 720                 };
 721
 722                 pinctrl_canfd1: canfd1grp-1 {
 723                         fsl,pins = <
 724                                 MX6SX_PAD_QSPI1B_DQS__CANFD_TX1         0x1b0b0
 725                                 MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1       0x1b0b0
 726                         >;
 727                 };
 728
 729                 pinctrl_canfd2: canfd2grp-1 {
 730                         fsl,pins = <
 731                                 MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2       0x1b0b0
 732                                 MX6SX_PAD_QSPI1A_DQS__CANFD_TX2         0x1b0b0
 733                         >;
 734                 };
 735
 736                 pinctrl_csi_0: csigrp-0 {
 737                         fsl,pins = <
 738                                 MX6SX_PAD_LCD1_DATA07__CSI1_MCLK        0x110b0
 739                                 MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK      0x110b0
 740                                 MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC       0x110b0
 741                                 MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC       0x110b0
 742                                 MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0      0x110b0
 743                                 MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1      0x110b0
 744                                 MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2      0x110b0
 745                                 MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3      0x110b0
 746                                 MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4      0x110b0
 747                                 MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5      0x110b0
 748                                 MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6      0x110b0
 749                                 MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7      0x110b0
 750                                 MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8      0x110b0
 751                                 MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9      0x110b0
 752                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27       0x80000000
 753                                 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28       0x80000000
 754                         >;
 755                 };
 756
 757                 pinctrl_egalax_int: egalax_intgrp {
 758                         fsl,pins = <
 759                                 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
 760                         >;
 761                 };
 762
 763                 pinctrl_enet1: enet1grp {
 764                         fsl,pins = <
 765                                 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
 766                                 MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
 767                                 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
 768                                 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
 769                                 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
 770                                 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
 771                                 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
 772                                 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
 773                                 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 774                                 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 775                                 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 776                                 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 777                                 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 778                                 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 779                                 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
 780                                 MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
 781                                 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
 782                         >;
 783                 };
 784
 785                 pinctrl_enet2: enet2grp {
 786                         fsl,pins = <
 787                                 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
 788                                 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
 789                                 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
 790                                 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
 791                                 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
 792                                 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
 793                                 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
 794                                 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
 795                                 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
 796                                 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
 797                                 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
 798                                 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
 799                         >;
 800                 };
 801
 802                 pinctrl_flexcan1: flexcan1grp {
 803                         fsl,pins = <
 804                                 MX6SX_PAD_QSPI1B_DQS__CAN1_TX           0x1b020
 805                                 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX         0x1b020
 806                         >;
 807                 };
 808
 809                 pinctrl_flexcan2: flexcan2grp {
 810                         fsl,pins = <
 811                                 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX         0x1b020
 812                                 MX6SX_PAD_QSPI1A_DQS__CAN2_TX           0x1b020
 813                         >;
 814                 };
 815
 816                 pinctrl_gpio_keys: gpio_keysgrp {
 817                         fsl,pins = <
 818                                 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
 819                                 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
 820                         >;
 821                 };
 822
 823                 pinctrl_can_gpios: can-gpios {
 824                         fsl,pins = <
 825                                 MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
 826                                 MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
 827                         >;
 828                 };
 829
 830                 pinctrl_i2c1: i2c1grp {
 831                         fsl,pins = <
 832                                 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
 833                                 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
 834                         >;
 835                 };
 836
 837                 pinctrl_i2c2: i2c2grp {
 838                         fsl,pins = <
 839                                 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
 840                                 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
 841                         >;
 842                 };
 843
 844                 pinctrl_i2c3: i2c3grp {
 845                         fsl,pins = <
 846                                 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
 847                                 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
 848                         >;
 849                 };
 850
 851                 pinctrl_i2c4: i2c4grp {
 852                         fsl,pins = <
 853                                 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
 854                                 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
 855                         >;
 856                 };
 857
 858                 pinctrl_lcdif_dat: lcdifdatgrp {
 859                         fsl,pins = <
 860                                 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
 861                                 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
 862                                 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
 863                                 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
 864                                 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
 865                                 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
 866                                 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
 867                                 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
 868                                 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
 869                                 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
 870                                 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
 871                                 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
 872                                 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
 873                                 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
 874                                 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
 875                                 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
 876                                 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
 877                                 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
 878                                 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
 879                                 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
 880                                 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
 881                                 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
 882                                 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
 883                                 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
 884                         >;
 885                 };
 886
 887                 pinctrl_lcdif_ctrl: lcdifctrlgrp {
 888                         fsl,pins = <
 889                                 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
 890                                 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
 891                                 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
 892                                 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
 893                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
 894                         >;
 895                 };
 896
 897                 pinctrl_pwm3: pwm3grp {
 898                         fsl,pins = <
 899                                 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
 900                         >;
 901                 };
 902
 903                 pinctrl_pwm4: pwm4grp {
 904                         fsl,pins = <
 905                                 MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
 906                         >;
 907                 };
 908
 909                 pinctrl_qspi2_1: qspi2grp_1 {
 910                         fsl,pins = <
 911                                 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
 912                                 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
 913                                 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
 914                                 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
 915                                 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
 916                                 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
 917                                 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
 918                                 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
 919                                 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
 920                                 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
 921                                 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
 922                                 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
 923                         >;
 924                 };
 925
 926                 pinctrl_sai1: sai1grp {
 927                         fsl,pins = <
 928                                 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x130b0
 929                                 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x130b0
 930                                 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x120b0
 931                                 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x130b0
 932                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK      0x130b0
 933                         >;
 934                 };
 935
 936                 pinctrl_spdif: spdifgrp {
 937                         fsl,pins = <
 938                                 MX6SX_PAD_SD4_DATA4__SPDIF_OUT          0x1b0b0
 939                         >;
 940                 };
 941
 942                 pinctrl_pcie: pciegrp {
 943                         fsl,pins = <
 944                                 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
 945                         >;
 946                 };
 947
 948                 pinctrl_pcie_reg: pciereggrp {
 949                         fsl,pins = <
 950                                 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
 951                         >;
 952                 };
 953
 954                 pinctrl_vcc_sd3: vccsd3grp {
 955                         fsl,pins = <
 956                                 MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
 957                         >;
 958                 };
 959
 960                 pinctrl_uart1: uart1grp {
 961                         fsl,pins = <
 962                                 MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 963                                 MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 964                         >;
 965                 };
 966
 967                 pinctrl_uart5: uart5grp {
 968                         fsl,pins = <
 969                                 MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
 970                                 MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
 971                                 MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
 972                                 MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
 973                         >;
 974                 };
 975
 976                 pinctrl_uart5dte_1: uart5dtegrp-1 {
 977                         fsl,pins = <
 978                                 MX6SX_PAD_KEY_ROW3__UART5_TX            0x1b0b1
 979                                 MX6SX_PAD_KEY_COL3__UART5_RX            0x1b0b1
 980                                 MX6SX_PAD_KEY_ROW2__UART5_RTS_B         0x1b0b1
 981                                 MX6SX_PAD_KEY_COL2__UART5_CTS_B         0x1b0b1
 982                         >;
 983                 };
 984
 985                 pinctrl_usb_otg1: usbotg1grp {
 986                         fsl,pins = <
 987                                 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
 988                         >;
 989                 };
 990
 991                 pinctrl_usb_otg1_id: usbotg1idgrp {
 992                         fsl,pins = <
 993                                 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
 994                         >;
 995                 };
 996
 997                 pinctrl_usb_otg2: usbot2ggrp {
 998                         fsl,pins = <
 999                                 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
1000                         >;
1001                 };
1002
1003                 pinctrl_usdhc2: usdhc2grp {
1004                         fsl,pins = <
1005                                 MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
1006                                 MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
1007                                 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
1008                                 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
1009                                 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
1010                                 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
1011                         >;
1012                 };
1013
1014                 pinctrl_usdhc3: usdhc3grp {
1015                         fsl,pins = <
1016                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17069
1017                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10071
1018                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17069
1019                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17069
1020                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17069
1021                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17069
1022                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17069
1023                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17069
1024                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17069
1025                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17069
1026                                 MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
1027                                 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
1028                         >;
1029                 };
1030
1031                 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
1032                         fsl,pins = <
1033                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
1034                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
1035                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
1036                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
1037                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
1038                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
1039                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
1040                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
1041                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
1042                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
1043                         >;
1044                 };
1045
1046                 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
1047                         fsl,pins = <
1048                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
1049                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
1050                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
1051                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
1052                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
1053                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
1054                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
1055                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
1056                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
1057                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
1058                         >;
1059                 };
1060
1061                 pinctrl_usdhc4: usdhc4grp {
1062                         fsl,pins = <
1063                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
1064                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
1065                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
1066                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
1067                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
1068                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
1069                                 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
1070                                 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
1071                         >;
1072                 };
1073
1074                 pinctrl_usdhc4_1: usdhc4grp-1 {
1075                         fsl,pins = <
1076                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
1077                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
1078                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
1079                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
1080                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
1081                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
1082                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x17059
1083                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x17059
1084                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x17059
1085                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x17059
1086                         >;
1087                 };
1088
1089                 pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
1090                         fsl,pins = <
1091                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170b9
1092                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100b9
1093                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170b9
1094                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170b9
1095                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170b9
1096                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170b9
1097                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170b9
1098                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170b9
1099                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170b9
1100                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170b9
1101                         >;
1102                 };
1103
1104                 pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
1105                         fsl,pins = <
1106                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170f9
1107                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100f9
1108                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170f9
1109                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170f9
1110                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170f9
1111                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170f9
1112                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170f9
1113                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170f9
1114                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170f9
1115                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170f9
1116                         >;
1117                 };
1118         };
1119 };