Merge branch 'late/dt' into next/dt2

This is support for the ARM Chromebook, originally scheduled
as a "late" pull request. Since it's already late now, we
can combine this into the existing next/dt2 branch.

* late/dt:
  ARM: exynos: dts: cros5250: add EC device
  ARM: dts: Add sbs-battery for exynos5250-snow
  ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
  ARM: dts: Add chip-id controller node on Exynos4/5 SoC
  ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree

diff --combined arch/arm/Kconfig
index 398a9fbcd4272ed04586ff9544c28e5159ecb1dd,be23497f5b2982b7c6c61bcfbe0324176a4c8ccc..60ee4f124af2f617f425826ba7d13f71f29c87d3
--- 1/arch/arm/Kconfig
--- 2/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -473,14 -473,12 +473,14 @@@ config ARCH_MX
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
 +      select CLKSRC_OF
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
        select HAVE_CLK_PREPARE
        select MULTI_IRQ_HANDLER
        select PINCTRL
        select SPARSE_IRQ
 +      select STMP_DEVICE
        select USE_OF
        help
          Support for Freescale MXS-based family of processors
@@@ -564,7 -562,6 +564,7 @@@ config ARCH_DOV
        select PINCTRL_DOVE
        select PLAT_ORION_LEGACY
        select USB_ARCH_HAS_EHCI
 +      select MVEBU_MBUS
        help
          Support for the Marvell Dove SoC 88AP510
  
@@@ -578,7 -575,6 +578,7 @@@ config ARCH_KIRKWOO
        select PINCTRL
        select PINCTRL_KIRKWOOD
        select PLAT_ORION_LEGACY
 +      select MVEBU_MBUS
        help
          Support for the following Marvell Kirkwood series SoCs:
          88F6180, 88F6192 and 88F6281.
@@@ -590,7 -586,6 +590,7 @@@ config ARCH_MV78XX
        select GENERIC_CLOCKEVENTS
        select PCI
        select PLAT_ORION_LEGACY
 +      select MVEBU_MBUS
        help
          Support for the following Marvell MV78xx0 series SoCs:
          MV781x0, MV782x0.
@@@ -603,7 -598,6 +603,7 @@@ config ARCH_ORION5
        select GENERIC_CLOCKEVENTS
        select PCI
        select PLAT_ORION_LEGACY
 +      select MVEBU_MBUS
        help
          Support for the following Marvell Orion 5x series SoCs:
          Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@@ -679,7 -673,6 +679,7 @@@ config ARCH_TEGR
        select HAVE_CLK
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
 +      select SOC_BUS
        select SPARSE_IRQ
        select USE_OF
        help
@@@ -1196,9 -1189,9 +1196,9 @@@ config ARM_NR_BANK
        default 8
  
  config IWMMXT
-       bool "Enable iWMMXt support"
+       bool "Enable iWMMXt support" if !CPU_PJ4
        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
-       default y if PXA27x || PXA3xx || ARCH_MMP
+       default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
        help
          Enable support for iWMMXt context switching at run time if
          running on a CPU that supports it.
@@@ -1452,6 -1445,16 +1452,16 @@@ config ARM_ERRATA_77542
         to deadlock. This workaround puts DSB before executing ISB if
         an abort may occur on cache maintenance.
  
+ config ARM_ERRATA_798181
+       bool "ARM errata: TLBI/DSB failure on Cortex-A15"
+       depends on CPU_V7 && SMP
+       help
+         On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
+         adequately shooting down all use of the old entries. This
+         option enables the Linux kernel workaround for this erratum
+         which sends an IPI to the CPUs that are running the same ASID
+         as the one being invalidated.
+ 
  endmenu
  
  source "arch/arm/common/Kconfig"
@@@ -1606,7 -1609,6 +1616,7 @@@ config HAVE_ARM_ARCH_TIME
  config HAVE_ARM_TWD
        bool
        depends on SMP
 +      select CLKSRC_OF if OF
        help
          This options enables support for the ARM timer and watchdog unit
  

diff --combined arch/arm/boot/dts/imx28-m28evk.dts
index 5f0ba99aa809d4c8309c80520bd7aa2be67e164e,fd36e1cca1042306476c54d4038603780af358a1..5aa44e05c9f5dd4df4204ea5af31601c234cf8ee
--- 1/arch/arm/boot/dts/imx28-m28evk.dts
--- 2/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@@ -119,32 -119,7 +119,32 @@@
                                pinctrl-names = "default";
                                pinctrl-0 = <&lcdif_24bit_pins_a
                                             &lcdif_pins_m28>;
 +                              display = <&display>;
                                status = "okay";
 +
 +                              display: display {
 +                                      bits-per-pixel = <16>;
 +                                      bus-width = <18>;
 +
 +                                      display-timings {
 +                                              native-mode = <&timing0>;
 +                                              timing0: timing0 {
 +                                                      clock-frequency = <33260000>;
 +                                                      hactive = <800>;
 +                                                      vactive = <480>;
 +                                                      hback-porch = <0>;
 +                                                      hfront-porch = <256>;
 +                                                      vback-porch = <0>;
 +                                                      vfront-porch = <45>;
 +                                                      hsync-len = <1>;
 +                                                      vsync-len = <1>;
 +                                                      hsync-active = <0>;
 +                                                      vsync-active = <0>;
 +                                                      de-active = <1>;
 +                                                      pixelclk-active = <1>;
 +                                              };
 +                                      };
 +                              };
                        };
  
                        can0: can@80032000 {
@@@ -177,7 -152,6 +177,6 @@@
                        i2c0: i2c@80058000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&i2c0_pins_a>;
-                               clock-frequency = <400000>;
                                status = "okay";
  
                                sgtl5000: codec@0a {
@@@ -246,8 -220,6 +245,8 @@@
                        phy-mode = "rmii";
                        pinctrl-names = "default";
                        pinctrl-0 = <&mac0_pins_a>;
 +                      clocks = <&clks 57>, <&clks 57>;
 +                      clock-names = "ipg", "ahb";
                        status = "okay";
                };
  

diff --combined arch/arm/boot/dts/imx6qdl.dtsi
index 59e970f74e8f44afd5af5bdc72407b0e992354ec,281a223591ff83d5a9eef96c6775c77c99a356ad..491b0a0c24b07a0d5ba3ff086070eab721f643ce
--- 1/arch/arm/boot/dts/imx6qdl.dtsi
--- 2/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@@ -65,13 -65,9 +65,13 @@@
                interrupt-parent = <&intc>;
                ranges;
  
 -              dma-apbh@00110000 {
 +              dma_apbh: dma-apbh@00110000 {
                        compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
                        reg = <0x00110000 0x2000>;
 +                      interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
 +                      interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 +                      #dma-cells = <1>;
 +                      dma-channels = <4>;
                        clocks = <&clks 106>;
                };
  
@@@ -87,8 -83,6 +87,8 @@@
                                 <&clks 150>, <&clks 149>;
                        clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
                                      "gpmi_bch_apb", "per1_bch";
 +                      dmas = <&dma_apbh 0>;
 +                      dma-names = "rx-tx";
                        fsl,gpmi-dma-channel = <0>;
                        status = "disabled";
                };
@@@ -97,6 -91,7 +97,7 @@@
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0x00a00600 0x20>;
                        interrupts = <1 13 0xf01>;
+                       clocks = <&clks 15>;
                };
  
                L2: l2-cache@00a02000 {

diff --combined arch/arm/mach-omap2/io.c
index 2bef5a7e6af806a05495d4e7d40de312bd6e160a,5c445ca1e271ca9f14c9e4fd008035ee449ad9b4..e210fa830f8d7d076fdec7a23202bdab8b1a2089
--- 1/arch/arm/mach-omap2/io.c
--- 2/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@@ -54,6 -54,12 +54,12 @@@
  #include "prm3xxx.h"
  #include "prm44xx.h"
  
+ /*
+  * omap_clk_init: points to a function that does the SoC-specific
+  * clock initializations
+  */
+ int (*omap_clk_init)(void);
+ 
  /*
   * The machine specific code may provide the extra mapping besides the
   * default mapping provided here.
@@@ -271,14 -277,6 +277,14 @@@ static struct map_desc omap54xx_io_desc
                .length         = L4_PER_54XX_SIZE,
                .type           = MT_DEVICE,
        },
 +#ifdef CONFIG_OMAP4_ERRATA_I688
 +      {
 +              .virtual        = OMAP4_SRAM_VA,
 +              .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
 +              .length         = PAGE_SIZE,
 +              .type           = MT_MEMORY_SO,
 +      },
 +#endif
  };
  #endif
  
@@@ -331,7 -329,6 +337,7 @@@ void __init omap4_map_io(void
  void __init omap5_map_io(void)
  {
        iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
 +      omap_barriers_init();
  }
  #endif
  /*
@@@ -406,7 -403,7 +412,7 @@@ void __init omap2420_init_early(void
        omap242x_clockdomains_init();
        omap2420_hwmod_init();
        omap_hwmod_init_postsetup();
-       omap2420_clk_init();
+       omap_clk_init = omap2420_clk_init;
  }
  
  void __init omap2420_init_late(void)
@@@ -436,7 -433,7 +442,7 @@@ void __init omap2430_init_early(void
        omap243x_clockdomains_init();
        omap2430_hwmod_init();
        omap_hwmod_init_postsetup();
-       omap2430_clk_init();
+       omap_clk_init = omap2430_clk_init;
  }
  
  void __init omap2430_init_late(void)
@@@ -471,7 -468,7 +477,7 @@@ void __init omap3_init_early(void
        omap3xxx_clockdomains_init();
        omap3xxx_hwmod_init();
        omap_hwmod_init_postsetup();
-       omap3xxx_clk_init();
+       omap_clk_init = omap3xxx_clk_init;
  }
  
  void __init omap3430_init_early(void)
@@@ -509,7 -506,7 +515,7 @@@ void __init ti81xx_init_early(void
        omap3xxx_clockdomains_init();
        omap3xxx_hwmod_init();
        omap_hwmod_init_postsetup();
-       omap3xxx_clk_init();
+       omap_clk_init = omap3xxx_clk_init;
  }
  
  void __init omap3_init_late(void)
@@@ -577,7 -574,7 +583,7 @@@ void __init am33xx_init_early(void
        am33xx_clockdomains_init();
        am33xx_hwmod_init();
        omap_hwmod_init_postsetup();
-       am33xx_clk_init();
+       omap_clk_init = am33xx_clk_init;
  }
  #endif
  
@@@ -602,7 -599,7 +608,7 @@@ void __init omap4430_init_early(void
        omap44xx_clockdomains_init();
        omap44xx_hwmod_init();
        omap_hwmod_init_postsetup();
-       omap4xxx_clk_init();
+       omap_clk_init = omap4xxx_clk_init;
  }
  
  void __init omap4430_init_late(void)

diff --combined arch/arm/mach-omap2/omap_hwmod.c
index 63b774fb8089b00e632e57aac55b12d6a575dfbb,a202a47851045c8be6d947ce6407574d7a824f27..39771c12d8b610a074ef5bb3705db24d56d07980
--- 1/arch/arm/mach-omap2/omap_hwmod.c
--- 2/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@@ -138,8 -138,6 +138,8 @@@
  #include <linux/spinlock.h>
  #include <linux/slab.h>
  #include <linux/bootmem.h>
 +#include <linux/of.h>
 +#include <linux/of_address.h>
  
  #include <asm/system_misc.h>
  
@@@ -612,6 -610,8 +612,6 @@@ static int _enable_wakeup(struct omap_h
  
        /* XXX test pwrdm_get_wken for this hwmod's subsystem */
  
 -      oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
 -
        return 0;
  }
  
@@@ -645,6 -645,8 +645,6 @@@ static int _disable_wakeup(struct omap_
  
        /* XXX test pwrdm_get_wken for this hwmod's subsystem */
  
 -      oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
 -
        return 0;
  }
  
@@@ -1366,7 -1368,9 +1366,9 @@@ static void _enable_sysc(struct omap_hw
        }
  
        if (sf & SYSC_HAS_MIDLEMODE) {
-               if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+               if (oh->flags & HWMOD_FORCE_MSTANDBY) {
+                       idlemode = HWMOD_IDLEMODE_FORCE;
+               } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
                        idlemode = HWMOD_IDLEMODE_NO;
                } else {
                        if (sf & SYSC_HAS_ENAWAKEUP)
@@@ -1438,7 -1442,8 +1440,8 @@@ static void _idle_sysc(struct omap_hwmo
        }
  
        if (sf & SYSC_HAS_MIDLEMODE) {
-               if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+               if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
+                   (oh->flags & HWMOD_FORCE_MSTANDBY)) {
                        idlemode = HWMOD_IDLEMODE_FORCE;
                } else {
                        if (sf & SYSC_HAS_ENAWAKEUP)
@@@ -2347,34 -2352,6 +2350,34 @@@ static int _shutdown(struct omap_hwmod 
        return 0;
  }
  
 +/**
 + * of_dev_hwmod_lookup - look up needed hwmod from dt blob
 + * @np: struct device_node *
 + * @oh: struct omap_hwmod *
 + *
 + * Parse the dt blob and find out needed hwmod. Recursive function is
 + * implemented to take care hierarchical dt blob parsing.
 + * Return: The device node on success or NULL on failure.
 + */
 +static struct device_node *of_dev_hwmod_lookup(struct device_node *np,
 +                                              struct omap_hwmod *oh)
 +{
 +      struct device_node *np0 = NULL, *np1 = NULL;
 +      const char *p;
 +
 +      for_each_child_of_node(np, np0) {
 +              if (of_find_property(np0, "ti,hwmods", NULL)) {
 +                      p = of_get_property(np0, "ti,hwmods", NULL);
 +                      if (!strcmp(p, oh->name))
 +                              return np0;
 +                      np1 = of_dev_hwmod_lookup(np0, oh);
 +                      if (np1)
 +                              return np1;
 +              }
 +      }
 +      return NULL;
 +}
 +
  /**
   * _init_mpu_rt_base - populate the virtual address for a hwmod
   * @oh: struct omap_hwmod * to locate the virtual address
@@@ -2387,8 -2364,7 +2390,8 @@@
  static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
  {
        struct omap_hwmod_addr_space *mem;
 -      void __iomem *va_start;
 +      void __iomem *va_start = NULL;
 +      struct device_node *np;
  
        if (!oh)
                return;
@@@ -2402,18 -2378,10 +2405,18 @@@
        if (!mem) {
                pr_debug("omap_hwmod: %s: no MPU register target found\n",
                         oh->name);
 -              return;
 +
 +              /* Extract the IO space from device tree blob */
 +              if (!of_have_populated_dt())
 +                      return;
 +
 +              np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
 +              if (np)
 +                      va_start = of_iomap(np, 0);
 +      } else {
 +              va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
        }
  
 -      va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
        if (!va_start) {
                pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
                return;
@@@ -2445,8 -2413,7 +2448,8 @@@ static int __init _init(struct omap_hwm
        if (oh->_state != _HWMOD_STATE_REGISTERED)
                return 0;
  
 -      _init_mpu_rt_base(oh, NULL);
 +      if (oh->class->sysc)
 +              _init_mpu_rt_base(oh, NULL);
  
        r = _init_clocks(oh, NULL);
        if (IS_ERR_VALUE(r)) {

diff --combined arch/arm/mach-omap2/omap_hwmod.h
index 28f4dea0512e85f50eb29deb69b4c613f420540f,d5dc935f6060446aee42a250eddbe6140e9aa42a..fe5962921f07244e602429b758f0d5ccecb7398c
--- 1/arch/arm/mach-omap2/omap_hwmod.h
--- 2/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@@ -427,8 -427,8 +427,8 @@@ struct omap_hwmod_omap4_prcm 
   *
   * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
   *     of idle, rather than relying on module smart-idle
-  * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
-  *     of standby, rather than relying on module smart-standby
+  * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
+  *     out of standby, rather than relying on module smart-standby
   * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
   *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
   *     XXX Should be HWMOD_SETUP_NO_RESET
@@@ -459,6 -459,10 +459,10 @@@
   *     correctly, or this is being abused to deal with some PM latency
   *     issues -- but we're currently suffering from a shortage of
   *     folks who are able to track these issues down properly.
+  * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
+  *     is kept in force-standby mode. Failing to do so causes PM problems
+  *     with musb on OMAP3630 at least. Note that musb has a dedicated register
+  *     to control MSTANDBY signal when MIDLEMODE is set to force-standby.
   */
  #define HWMOD_SWSUP_SIDLE                     (1 << 0)
  #define HWMOD_SWSUP_MSTANDBY                  (1 << 1)
@@@ -471,19 -475,22 +475,20 @@@
  #define HWMOD_16BIT_REG                               (1 << 8)
  #define HWMOD_EXT_OPT_MAIN_CLK                        (1 << 9)
  #define HWMOD_BLOCK_WFI                               (1 << 10)
+ #define HWMOD_FORCE_MSTANDBY                  (1 << 11)
  
  /*
   * omap_hwmod._int_flags definitions
   * These are for internal use only and are managed by the omap_hwmod code.
   *
   * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
 - * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
   * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
   * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
   *     causes the first call to _enable() to only update the pinmux
   */
  #define _HWMOD_NO_MPU_PORT                    (1 << 0)
 -#define _HWMOD_WAKEUP_ENABLED                 (1 << 1)
 -#define _HWMOD_SYSCONFIG_LOADED                       (1 << 2)
 -#define _HWMOD_SKIP_ENABLE                    (1 << 3)
 +#define _HWMOD_SYSCONFIG_LOADED                       (1 << 1)
 +#define _HWMOD_SKIP_ENABLE                    (1 << 2)
  
  /*
   * omap_hwmod._state definitions

diff --combined arch/arm/mach-omap2/timer.c
index 58d86d7abada1e083b0c8228715ef595ff3d8852,f62b509ed08de75e6f4191bc8cf43dc130c7cb2d..95e79a582f580d56e606f5468665ed0006659f8b
--- 1/arch/arm/mach-omap2/timer.c
--- 2/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@@ -62,7 -62,6 +62,7 @@@
  #define OMAP2_MPU_SOURCE      "sys_ck"
  #define OMAP3_MPU_SOURCE      OMAP2_MPU_SOURCE
  #define OMAP4_MPU_SOURCE      "sys_clkin_ck"
 +#define OMAP5_MPU_SOURCE      "sys_clkin"
  #define OMAP2_32K_SOURCE      "func_32k_ck"
  #define OMAP3_32K_SOURCE      "omap_32k_fck"
  #define OMAP4_32K_SOURCE      "sys_32k_ck"
@@@ -144,12 -143,7 +144,12 @@@ static struct property device_disabled 
  };
  
  static struct of_device_id omap_timer_match[] __initdata = {
 -      { .compatible = "ti,omap2-timer", },
 +      { .compatible = "ti,omap2420-timer", },
 +      { .compatible = "ti,omap3430-timer", },
 +      { .compatible = "ti,omap4430-timer", },
 +      { .compatible = "ti,omap5430-timer", },
 +      { .compatible = "ti,am335x-timer", },
 +      { .compatible = "ti,am335x-timer-1ms", },
        { }
  };
  
@@@ -493,7 -487,7 +493,7 @@@ static void __init realtime_counter_ini
                pr_err("%s: ioremap failed\n", __func__);
                return;
        }
 -      sys_clk = clk_get(NULL, "sys_clkin_ck");
 +      sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
        if (IS_ERR(sys_clk)) {
                pr_err("%s: failed to get system clock handle\n", __func__);
                iounmap(base);
@@@ -553,6 -547,8 +553,8 @@@ static inline void __init realtime_coun
                               clksrc_nr, clksrc_src)                   \
  void __init omap##name##_gptimer_timer_init(void)                     \
  {                                                                     \
+       if (omap_clk_init)                                              \
+               omap_clk_init();                                        \
        omap_dmtimer_init();                                            \
        omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
@@@ -562,6 -558,8 +564,8 @@@
                                clksrc_nr, clksrc_src)                  \
  void __init omap##name##_sync32k_timer_init(void)             \
  {                                                                     \
+       if (omap_clk_init)                                              \
+               omap_clk_init();                                        \
        omap_dmtimer_init();                                            \
        omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
        /* Enable the use of clocksource="gp_timer" kernel parameter */ \
@@@ -603,7 -601,7 +607,7 @@@ void __init omap4_local_timer_init(void
                int err;
  
                if (of_have_populated_dt()) {
 -                      twd_local_timer_of_register();
 +                      clocksource_of_init();
                        return;
                }
  
@@@ -622,7 -620,7 +626,7 @@@ void __init omap4_local_timer_init(void
  
  #ifdef CONFIG_SOC_OMAP5
  OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
 -                      2, OMAP4_MPU_SOURCE);
 +                      2, OMAP5_MPU_SOURCE);
  void __init omap5_realtime_timer_init(void)
  {
        int err;

diff --combined drivers/clk/tegra/clk-tegra20.c
index b0405b67f49c710843e9d16d46930f015f25bf59,f873dcefe0de63b4271ac82302a24892dbe4803d..8292a00c3de9f1dbae8b19e23b6ac45b3d275866
--- 1/drivers/clk/tegra/clk-tegra20.c
--- 2/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@@ -86,8 -86,8 +86,8 @@@
  #define PLLE_BASE 0xe8
  #define PLLE_MISC 0xec
  
 -#define PLL_BASE_LOCK 27
 -#define PLLE_MISC_LOCK 11
 +#define PLL_BASE_LOCK BIT(27)
 +#define PLLE_MISC_LOCK BIT(11)
  
  #define PLL_MISC_LOCK_ENABLE 18
  #define PLLDU_MISC_LOCK_ENABLE 22
@@@ -236,7 -236,7 +236,7 @@@ enum tegra20_clk 
        dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
        usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
        pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
 -      iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
 +      iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
        uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
        osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
        pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
@@@ -248,125 -248,125 +248,125 @@@ static struct clk *clks[clk_max]
  static struct clk_onecell_data clk_data;
  
  static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
 -      { 12000000, 600000000, 600, 12, 1, 8 },
 -      { 13000000, 600000000, 600, 13, 1, 8 },
 -      { 19200000, 600000000, 500, 16, 1, 6 },
 -      { 26000000, 600000000, 600, 26, 1, 8 },
 +      { 12000000, 600000000, 600, 12, 0, 8 },
 +      { 13000000, 600000000, 600, 13, 0, 8 },
 +      { 19200000, 600000000, 500, 16, 0, 6 },
 +      { 26000000, 600000000, 600, 26, 0, 8 },
        { 0, 0, 0, 0, 0, 0 },
  };
  
  static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
 -      { 12000000, 666000000, 666, 12, 1, 8},
 -      { 13000000, 666000000, 666, 13, 1, 8},
 -      { 19200000, 666000000, 555, 16, 1, 8},
 -      { 26000000, 666000000, 666, 26, 1, 8},
 -      { 12000000, 600000000, 600, 12, 1, 8},
 -      { 13000000, 600000000, 600, 13, 1, 8},
 -      { 19200000, 600000000, 375, 12, 1, 6},
 -      { 26000000, 600000000, 600, 26, 1, 8},
 +      { 12000000, 666000000, 666, 12, 0, 8},
 +      { 13000000, 666000000, 666, 13, 0, 8},
 +      { 19200000, 666000000, 555, 16, 0, 8},
 +      { 26000000, 666000000, 666, 26, 0, 8},
 +      { 12000000, 600000000, 600, 12, 0, 8},
 +      { 13000000, 600000000, 600, 13, 0, 8},
 +      { 19200000, 600000000, 375, 12, 0, 6},
 +      { 26000000, 600000000, 600, 26, 0, 8},
        { 0, 0, 0, 0, 0, 0 },
  };
  
  static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
 -      { 12000000, 216000000, 432, 12, 2, 8},
 -      { 13000000, 216000000, 432, 13, 2, 8},
 -      { 19200000, 216000000, 90,   4, 2, 1},
 -      { 26000000, 216000000, 432, 26, 2, 8},
 -      { 12000000, 432000000, 432, 12, 1, 8},
 -      { 13000000, 432000000, 432, 13, 1, 8},
 -      { 19200000, 432000000, 90,   4, 1, 1},
 -      { 26000000, 432000000, 432, 26, 1, 8},
 +      { 12000000, 216000000, 432, 12, 1, 8},
 +      { 13000000, 216000000, 432, 13, 1, 8},
 +      { 19200000, 216000000, 90,   4, 1, 1},
 +      { 26000000, 216000000, 432, 26, 1, 8},
 +      { 12000000, 432000000, 432, 12, 0, 8},
 +      { 13000000, 432000000, 432, 13, 0, 8},
 +      { 19200000, 432000000, 90,   4, 0, 1},
 +      { 26000000, 432000000, 432, 26, 0, 8},
        { 0, 0, 0, 0, 0, 0 },
  };
  
  static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
 -      { 28800000, 56448000, 49, 25, 1, 1},
 -      { 28800000, 73728000, 64, 25, 1, 1},
 -      { 28800000, 24000000,  5,  6, 1, 1},
 +      { 28800000, 56448000, 49, 25, 0, 1},
 +      { 28800000, 73728000, 64, 25, 0, 1},
 +      { 28800000, 24000000,  5,  6, 0, 1},
        { 0, 0, 0, 0, 0, 0 },
  };
  
  static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
 -      { 12000000, 216000000, 216, 12, 1, 4},
 -      { 13000000, 216000000, 216, 13, 1, 4},
 -      { 19200000, 216000000, 135, 12, 1, 3},
 -      { 26000000, 216000000, 216, 26, 1, 4},
 +      { 12000000, 216000000, 216, 12, 0, 4},
 +      { 13000000, 216000000, 216, 13, 0, 4},
 +      { 19200000, 216000000, 135, 12, 0, 3},
 +      { 26000000, 216000000, 216, 26, 0, 4},
  
 -      { 12000000, 594000000, 594, 12, 1, 8},
 -      { 13000000, 594000000, 594, 13, 1, 8},
 -      { 19200000, 594000000, 495, 16, 1, 8},
 -      { 26000000, 594000000, 594, 26, 1, 8},
 +      { 12000000, 594000000, 594, 12, 0, 8},
 +      { 13000000, 594000000, 594, 13, 0, 8},
 +      { 19200000, 594000000, 495, 16, 0, 8},
 +      { 26000000, 594000000, 594, 26, 0, 8},
  
 -      { 12000000, 1000000000, 1000, 12, 1, 12},
 -      { 13000000, 1000000000, 1000, 13, 1, 12},
 -      { 19200000, 1000000000, 625,  12, 1, 8},
 -      { 26000000, 1000000000, 1000, 26, 1, 12},
 +      { 12000000, 1000000000, 1000, 12, 0, 12},
 +      { 13000000, 1000000000, 1000, 13, 0, 12},
 +      { 19200000, 1000000000, 625,  12, 0, 8},
 +      { 26000000, 1000000000, 1000, 26, 0, 12},
  
        { 0, 0, 0, 0, 0, 0 },
  };
  
  static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
 -      { 12000000, 480000000, 960, 12, 2, 0},
 -      { 13000000, 480000000, 960, 13, 2, 0},
 -      { 19200000, 480000000, 200, 4,  2, 0},
 -      { 26000000, 480000000, 960, 26, 2, 0},
 +      { 12000000, 480000000, 960, 12, 0, 0},
 +      { 13000000, 480000000, 960, 13, 0, 0},
 +      { 19200000, 480000000, 200, 4,  0, 0},
 +      { 26000000, 480000000, 960, 26, 0, 0},
        { 0, 0, 0, 0, 0, 0 },
  };
  
  static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
        /* 1 GHz */
 -      { 12000000, 1000000000, 1000, 12, 1, 12},
 -      { 13000000, 1000000000, 1000, 13, 1, 12},
 -      { 19200000, 1000000000, 625,  12, 1, 8},
 -      { 26000000, 1000000000, 1000, 26, 1, 12},
 +      { 12000000, 1000000000, 1000, 12, 0, 12},
 +      { 13000000, 1000000000, 1000, 13, 0, 12},
 +      { 19200000, 1000000000, 625,  12, 0, 8},
 +      { 26000000, 1000000000, 1000, 26, 0, 12},
  
        /* 912 MHz */
 -      { 12000000, 912000000,  912,  12, 1, 12},
 -      { 13000000, 912000000,  912,  13, 1, 12},
 -      { 19200000, 912000000,  760,  16, 1, 8},
 -      { 26000000, 912000000,  912,  26, 1, 12},
 +      { 12000000, 912000000,  912,  12, 0, 12},
 +      { 13000000, 912000000,  912,  13, 0, 12},
 +      { 19200000, 912000000,  760,  16, 0, 8},
 +      { 26000000, 912000000,  912,  26, 0, 12},
  
        /* 816 MHz */
 -      { 12000000, 816000000,  816,  12, 1, 12},
 -      { 13000000, 816000000,  816,  13, 1, 12},
 -      { 19200000, 816000000,  680,  16, 1, 8},
 -      { 26000000, 816000000,  816,  26, 1, 12},
 +      { 12000000, 816000000,  816,  12, 0, 12},
 +      { 13000000, 816000000,  816,  13, 0, 12},
 +      { 19200000, 816000000,  680,  16, 0, 8},
 +      { 26000000, 816000000,  816,  26, 0, 12},
  
        /* 760 MHz */
 -      { 12000000, 760000000,  760,  12, 1, 12},
 -      { 13000000, 760000000,  760,  13, 1, 12},
 -      { 19200000, 760000000,  950,  24, 1, 8},
 -      { 26000000, 760000000,  760,  26, 1, 12},
 +      { 12000000, 760000000,  760,  12, 0, 12},
 +      { 13000000, 760000000,  760,  13, 0, 12},
 +      { 19200000, 760000000,  950,  24, 0, 8},
 +      { 26000000, 760000000,  760,  26, 0, 12},
  
        /* 750 MHz */
 -      { 12000000, 750000000,  750,  12, 1, 12},
 -      { 13000000, 750000000,  750,  13, 1, 12},
 -      { 19200000, 750000000,  625,  16, 1, 8},
 -      { 26000000, 750000000,  750,  26, 1, 12},
 +      { 12000000, 750000000,  750,  12, 0, 12},
 +      { 13000000, 750000000,  750,  13, 0, 12},
 +      { 19200000, 750000000,  625,  16, 0, 8},
 +      { 26000000, 750000000,  750,  26, 0, 12},
  
        /* 608 MHz */
 -      { 12000000, 608000000,  608,  12, 1, 12},
 -      { 13000000, 608000000,  608,  13, 1, 12},
 -      { 19200000, 608000000,  380,  12, 1, 8},
 -      { 26000000, 608000000,  608,  26, 1, 12},
 +      { 12000000, 608000000,  608,  12, 0, 12},
 +      { 13000000, 608000000,  608,  13, 0, 12},
 +      { 19200000, 608000000,  380,  12, 0, 8},
 +      { 26000000, 608000000,  608,  26, 0, 12},
  
        /* 456 MHz */
 -      { 12000000, 456000000,  456,  12, 1, 12},
 -      { 13000000, 456000000,  456,  13, 1, 12},
 -      { 19200000, 456000000,  380,  16, 1, 8},
 -      { 26000000, 456000000,  456,  26, 1, 12},
 +      { 12000000, 456000000,  456,  12, 0, 12},
 +      { 13000000, 456000000,  456,  13, 0, 12},
 +      { 19200000, 456000000,  380,  16, 0, 8},
 +      { 26000000, 456000000,  456,  26, 0, 12},
  
        /* 312 MHz */
 -      { 12000000, 312000000,  312,  12, 1, 12},
 -      { 13000000, 312000000,  312,  13, 1, 12},
 -      { 19200000, 312000000,  260,  16, 1, 8},
 -      { 26000000, 312000000,  312,  26, 1, 12},
 +      { 12000000, 312000000,  312,  12, 0, 12},
 +      { 13000000, 312000000,  312,  13, 0, 12},
 +      { 19200000, 312000000,  260,  16, 0, 8},
 +      { 26000000, 312000000,  312,  26, 0, 12},
  
        { 0, 0, 0, 0, 0, 0 },
  };
  
  static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
 -      { 12000000, 100000000,  200,  24, 1, 0 },
 +      { 12000000, 100000000,  200,  24, 0, 0 },
        { 0, 0, 0, 0, 0, 0 },
  };
  
@@@ -380,7 -380,7 +380,7 @@@ static struct tegra_clk_pll_params pll_
        .vco_max = 1400000000,
        .base_reg = PLLC_BASE,
        .misc_reg = PLLC_MISC,
 -      .lock_bit_idx = PLL_BASE_LOCK,
 +      .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
  };
@@@ -394,7 -394,7 +394,7 @@@ static struct tegra_clk_pll_params pll_
        .vco_max = 1200000000,
        .base_reg = PLLM_BASE,
        .misc_reg = PLLM_MISC,
 -      .lock_bit_idx = PLL_BASE_LOCK,
 +      .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
  };
@@@ -408,7 -408,7 +408,7 @@@ static struct tegra_clk_pll_params pll_
        .vco_max = 1400000000,
        .base_reg = PLLP_BASE,
        .misc_reg = PLLP_MISC,
 -      .lock_bit_idx = PLL_BASE_LOCK,
 +      .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
  };
@@@ -422,7 -422,7 +422,7 @@@ static struct tegra_clk_pll_params pll_
        .vco_max = 1400000000,
        .base_reg = PLLA_BASE,
        .misc_reg = PLLA_MISC,
 -      .lock_bit_idx = PLL_BASE_LOCK,
 +      .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
  };
@@@ -436,17 -436,11 +436,17 @@@ static struct tegra_clk_pll_params pll_
        .vco_max = 1000000000,
        .base_reg = PLLD_BASE,
        .misc_reg = PLLD_MISC,
 -      .lock_bit_idx = PLL_BASE_LOCK,
 +      .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
        .lock_delay = 1000,
  };
  
 +static struct pdiv_map pllu_p[] = {
 +      { .pdiv = 1, .hw_val = 1 },
 +      { .pdiv = 2, .hw_val = 0 },
 +      { .pdiv = 0, .hw_val = 0 },
 +};
 +
  static struct tegra_clk_pll_params pll_u_params = {
        .input_min = 2000000,
        .input_max = 40000000,
@@@ -456,10 -450,9 +456,10 @@@
        .vco_max = 960000000,
        .base_reg = PLLU_BASE,
        .misc_reg = PLLU_MISC,
 -      .lock_bit_idx = PLL_BASE_LOCK,
 +      .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
        .lock_delay = 1000,
 +      .pdiv_tohw = pllu_p,
  };
  
  static struct tegra_clk_pll_params pll_x_params = {
@@@ -471,7 -464,7 +471,7 @@@
        .vco_max = 1200000000,
        .base_reg = PLLX_BASE,
        .misc_reg = PLLX_MISC,
 -      .lock_bit_idx = PLL_BASE_LOCK,
 +      .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
  };
@@@ -485,7 -478,7 +485,7 @@@ static struct tegra_clk_pll_params pll_
        .vco_max = 0,
        .base_reg = PLLE_BASE,
        .misc_reg = PLLE_MISC,
 -      .lock_bit_idx = PLLE_MISC_LOCK,
 +      .lock_mask = PLLE_MISC_LOCK,
        .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
        .lock_delay = 0,
  };
@@@ -710,7 -703,7 +710,7 @@@ static void tegra20_pll_init(void
        clks[pll_a_out0] = clk;
  
        /* PLLE */
-       clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL,
+       clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
                             0, 100000000, &pll_e_params,
                             0, pll_e_freq_table, NULL);
        clk_register_clkdev(clk, "pll_e", NULL);
@@@ -718,8 -711,8 +718,8 @@@
  }
  
  static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
 -                                    "pll_p_cclk", "pll_p_out4_cclk",
 -                                    "pll_p_out3_cclk", "clk_d", "pll_x" };
 +                                    "pll_p", "pll_p_out4",
 +                                    "pll_p_out3", "clk_d", "pll_x" };
  static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
                                      "pll_p_out3", "pll_p_out2", "clk_d",
                                      "clk_32k", "pll_m_out1" };
@@@ -728,6 -721,38 +728,6 @@@ static void tegra20_super_clk_init(void
  {
        struct clk *clk;
  
 -      /*
 -       * DIV_U71 dividers for CCLK, these dividers are used only
 -       * if parent clock is fixed rate.
 -       */
 -
 -      /*
 -       * Clock input to cclk divided from pll_p using
 -       * U71 divider of cclk.
 -       */
 -      clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
 -                              clk_base + SUPER_CCLK_DIVIDER, 0,
 -                              TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
 -      clk_register_clkdev(clk, "pll_p_cclk", NULL);
 -
 -      /*
 -       * Clock input to cclk divided from pll_p_out3 using
 -       * U71 divider of cclk.
 -       */
 -      clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
 -                              clk_base + SUPER_CCLK_DIVIDER, 0,
 -                              TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
 -      clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
 -
 -      /*
 -       * Clock input to cclk divided from pll_p_out4 using
 -       * U71 divider of cclk.
 -       */
 -      clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
 -                              clk_base + SUPER_CCLK_DIVIDER, 0,
 -                              TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
 -      clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
 -
        /* CCLK */
        clk = tegra_clk_register_super_mux("cclk", cclk_parents,
                              ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
@@@ -1019,7 -1044,7 +1019,7 @@@ static void __init tegra20_periph_clk_i
                data = &tegra_periph_clk_list[i];
                clk = tegra_clk_register_periph(data->name, data->parent_names,
                                data->num_parents, &data->periph,
 -                              clk_base, data->offset);
 +                              clk_base, data->offset, data->flags);
                clk_register_clkdev(clk, data->con_id, data->dev_id);
                clks[data->clk_id] = clk;
        }
@@@ -1254,16 -1279,9 +1254,16 @@@ static __initdata struct tegra_clk_init
        {host1x, pll_c, 150000000, 0},
        {disp1, pll_p, 600000000, 0},
        {disp2, pll_p, 600000000, 0},
 +      {gr2d, pll_c, 300000000, 0},
 +      {gr3d, pll_c, 300000000, 0},
        {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
  };
  
 +static void __init tegra20_clock_apply_init_table(void)
 +{
 +      tegra_init_from_table(init_table, clks, clk_max);
 +}
 +
  /*
   * Some clocks may be used by different drivers depending on the board
   * configuration.  List those here to register them twice in the clock lookup
@@@ -1330,7 -1348,7 +1330,7 @@@ void __init tegra20_clock_init(struct d
        clk_data.clk_num = ARRAY_SIZE(clks);
        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
  
 -      tegra_init_from_table(init_table, clks, clk_max);
 +      tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
  
        tegra_cpu_car_ops = &tegra20_cpu_car_ops;
  }

diff --combined drivers/net/ethernet/freescale/fec.c
index dd098ea44d4881543f1ab6b708dc5ce3c767ffe2,f292c3aa423fbdeabb83ebdafa3b1699e988b19a..cb5783d4b1e09f221d43fe3e69f4d0a2ea1744b2
--- 1/drivers/net/ethernet/freescale/fec.c
--- 2/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@@ -345,6 -345,53 +345,53 @@@ fec_enet_start_xmit(struct sk_buff *skb
        return NETDEV_TX_OK;
  }
  
+ /* Init RX & TX buffer descriptors
+  */
+ static void fec_enet_bd_init(struct net_device *dev)
+ {
+       struct fec_enet_private *fep = netdev_priv(dev);
+       struct bufdesc *bdp;
+       unsigned int i;
+ 
+       /* Initialize the receive buffer descriptors. */
+       bdp = fep->rx_bd_base;
+       for (i = 0; i < RX_RING_SIZE; i++) {
+ 
+               /* Initialize the BD for every fragment in the page. */
+               if (bdp->cbd_bufaddr)
+                       bdp->cbd_sc = BD_ENET_RX_EMPTY;
+               else
+                       bdp->cbd_sc = 0;
+               bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
+       }
+ 
+       /* Set the last buffer to wrap */
+       bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
+       bdp->cbd_sc |= BD_SC_WRAP;
+ 
+       fep->cur_rx = fep->rx_bd_base;
+ 
+       /* ...and the same for transmit */
+       bdp = fep->tx_bd_base;
+       fep->cur_tx = bdp;
+       for (i = 0; i < TX_RING_SIZE; i++) {
+ 
+               /* Initialize the BD for every fragment in the page. */
+               bdp->cbd_sc = 0;
+               if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
+                       dev_kfree_skb_any(fep->tx_skbuff[i]);
+                       fep->tx_skbuff[i] = NULL;
+               }
+               bdp->cbd_bufaddr = 0;
+               bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
+       }
+ 
+       /* Set the last buffer to wrap */
+       bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
+       bdp->cbd_sc |= BD_SC_WRAP;
+       fep->dirty_tx = bdp;
+ }
+ 
  /* This function is called to start or restart the FEC during a link
   * change.  This only happens when switching between half and full
   * duplex.
@@@ -388,6 -435,8 +435,8 @@@ fec_restart(struct net_device *ndev, in
        /* Set maximum receive buffer size. */
        writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
  
+       fec_enet_bd_init(ndev);
+ 
        /* Set receive and transmit descriptor base. */
        writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
        if (fep->bufdesc_ex)
@@@ -397,7 -446,6 +446,6 @@@
                writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
                        * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
  
-       fep->cur_rx = fep->rx_bd_base;
  
        for (i = 0; i <= TX_RING_MOD_MASK; i++) {
                if (fep->tx_skbuff[i]) {
@@@ -1597,8 -1645,6 +1645,6 @@@ static int fec_enet_init(struct net_dev
  {
        struct fec_enet_private *fep = netdev_priv(ndev);
        struct bufdesc *cbd_base;
-       struct bufdesc *bdp;
-       unsigned int i;
  
        /* Allocate memory for buffer descriptors. */
        cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
@@@ -1608,6 -1654,7 +1654,7 @@@
                return -ENOMEM;
        }
  
+       memset(cbd_base, 0, PAGE_SIZE);
        spin_lock_init(&fep->hw_lock);
  
        fep->netdev = ndev;
@@@ -1631,35 -1678,6 +1678,6 @@@
        writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
        netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
  
-       /* Initialize the receive buffer descriptors. */
-       bdp = fep->rx_bd_base;
-       for (i = 0; i < RX_RING_SIZE; i++) {
- 
-               /* Initialize the BD for every fragment in the page. */
-               bdp->cbd_sc = 0;
-               bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
-       }
- 
-       /* Set the last buffer to wrap */
-       bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
-       bdp->cbd_sc |= BD_SC_WRAP;
- 
-       /* ...and the same for transmit */
-       bdp = fep->tx_bd_base;
-       fep->cur_tx = bdp;
-       for (i = 0; i < TX_RING_SIZE; i++) {
- 
-               /* Initialize the BD for every fragment in the page. */
-               bdp->cbd_sc = 0;
-               bdp->cbd_bufaddr = 0;
-               bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
-       }
- 
-       /* Set the last buffer to wrap */
-       bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
-       bdp->cbd_sc |= BD_SC_WRAP;
-       fep->dirty_tx = bdp;
- 
        fec_restart(ndev, 0);
  
        return 0;
@@@ -1802,23 -1820,18 +1820,23 @@@ fec_probe(struct platform_device *pdev
                goto failed_clk;
        }
  
 +      /* enet_out is optional, depends on board */
 +      fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
 +      if (IS_ERR(fep->clk_enet_out))
 +              fep->clk_enet_out = NULL;
 +
        fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
        fep->bufdesc_ex =
                pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
        if (IS_ERR(fep->clk_ptp)) {
 -              ret = PTR_ERR(fep->clk_ptp);
 +              fep->clk_ptp = NULL;
                fep->bufdesc_ex = 0;
        }
  
        clk_prepare_enable(fep->clk_ahb);
        clk_prepare_enable(fep->clk_ipg);
 -      if (!IS_ERR(fep->clk_ptp))
 -              clk_prepare_enable(fep->clk_ptp);
 +      clk_prepare_enable(fep->clk_enet_out);
 +      clk_prepare_enable(fep->clk_ptp);
  
        reg_phy = devm_regulator_get(&pdev->dev, "phy");
        if (!IS_ERR(reg_phy)) {
@@@ -1883,8 -1896,8 +1901,8 @@@ failed_irq
  failed_regulator:
        clk_disable_unprepare(fep->clk_ahb);
        clk_disable_unprepare(fep->clk_ipg);
 -      if (!IS_ERR(fep->clk_ptp))
 -              clk_disable_unprepare(fep->clk_ptp);
 +      clk_disable_unprepare(fep->clk_enet_out);
 +      clk_disable_unprepare(fep->clk_ptp);
  failed_pin:
  failed_clk:
        iounmap(fep->hwp);
@@@ -1910,7 -1923,6 +1928,7 @@@ fec_drv_remove(struct platform_device *
        clk_disable_unprepare(fep->clk_ptp);
        if (fep->ptp_clock)
                ptp_clock_unregister(fep->ptp_clock);
 +      clk_disable_unprepare(fep->clk_enet_out);
        clk_disable_unprepare(fep->clk_ahb);
        clk_disable_unprepare(fep->clk_ipg);
        for (i = 0; i < FEC_IRQ_NUM; i++) {
@@@ -1941,7 -1953,6 +1959,7 @@@ fec_suspend(struct device *dev
                fec_stop(ndev);
                netif_device_detach(ndev);
        }
 +      clk_disable_unprepare(fep->clk_enet_out);
        clk_disable_unprepare(fep->clk_ahb);
        clk_disable_unprepare(fep->clk_ipg);
  
@@@ -1954,7 -1965,6 +1972,7 @@@ fec_resume(struct device *dev
        struct net_device *ndev = dev_get_drvdata(dev);
        struct fec_enet_private *fep = netdev_priv(ndev);
  
 +      clk_prepare_enable(fep->clk_enet_out);
        clk_prepare_enable(fep->clk_ahb);
        clk_prepare_enable(fep->clk_ipg);
        if (netif_running(ndev)) {