1 #ifndef _CYGONCE_ETH_FEC_H_
2 #define _CYGONCE_ETH_FEC_H_
3 //==========================================================================
7 // Fast Ethernet MAC controller in i.MXx
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
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32 // License. However the source code for this file must still be made available
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39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //####BSDCOPYRIGHTBEGIN####
45 //####BSDCOPYRIGHTEND####
46 //==========================================================================
47 //#####DESCRIPTIONBEGIN####
49 // Author(s): Fred Fan
55 //####DESCRIPTIONEND####
57 //==========================================================================
59 #include <cyg/infra/cyg_type.h>
61 #include <cyg/hal/hal_io.h>
62 /* The defines of event bits */
63 #define FEC_EVENT_HBERR 0x80000000
64 #define FEC_EVENT_BABR 0x40000000
65 #define FEC_EVENT_BABT 0x20000000
66 #define FEC_EVENT_GRA 0x10000000
67 #define FEC_EVENT_TXF 0x08000000
68 #define FEC_EVENT_TXB 0x04000000
69 #define FEC_EVENT_RXF 0x02000000
70 #define FEC_EVENT_RXB 0x01000000
71 #define FEC_EVENT_MII 0x00800000
72 #define FEC_EVENT_EBERR 0x00400000
73 #define FEC_EVENT_LC 0x00200000
74 #define FEC_EVENT_RL 0x00100000
75 #define FEC_EVENT_UN 0x00080000
77 #define FEC_EVENT_TX FEC_EVENT_TXF
78 #define FEC_EVENT_TX_ERR (FEC_EVENT_BABT | FEC_EVENT_LC | FEC_EVENT_RL | FEC_EVENT_UN)
79 #define FEC_EVENT_RX FEC_EVENT_RXF
80 #define FEC_EVENT_ERR (FEC_EVENT_HBERR | FEC_EVENT_EBERR)
82 #define FEC_RX_FRAMES ((CYGNUM_IO_ETH_DRIVERS_NUM_PKT/2)+1)
83 #define FEC_FRAME_LEN (1540+4)
85 /* the defines to active transmit or receive frame */
86 #define FEC_RX_TX_ACTIVE 0x01000000
88 /* the defines of Ethernet Control register */
89 #define FEC_RESET 0x00000001
90 #define FEC_ETHER_EN 0x00000002
92 /* the defins of MII operation */
93 #define FEC_MII_ST 0x40000000
94 #define FEC_MII_OP_OFF 28
95 #define FEC_MII_OP_MASK 0x03
96 #define FEC_MII_OP_RD 0x02
97 #define FEC_MII_OP_WR 0x01
98 #define FEC_MII_PA_OFF 23
99 #define FEC_MII_PA_MASK 0xFF
100 #define FEC_MII_RA_OFF 18
101 #define FEC_MII_RA_MASK 0xFF
102 #define FEC_MII_TA 0x00020000
103 #define FEC_MII_DATA_OFF 0
104 #define FEC_MII_DATA_MASK 0x0000FFFF
106 #define FEC_MII_FRAME ( FEC_MII_ST | FEC_MII_TA )
107 #define FEC_MII_OP(x) ( ((x) & FEC_MII_OP_MASK) << FEC_MII_OP_OFF )
108 #define FEC_MII_PA(pa) (((pa)& FEC_MII_PA_MASK) << FEC_MII_PA_OFF)
109 #define FEC_MII_RA(ra) (((ra)& FEC_MII_RA_MASK) << FEC_MII_RA_OFF)
110 #define FEC_MII_SET_DATA(v) (((v) & FEC_MII_DATA_MASK) << FEC_MII_DATA_OFF)
111 #define FEC_MII_GET_DATA(v) (((v) >> FEC_MII_DATA_OFF) & FEC_MII_DATA_MASK )
112 #define FEC_MII_READ(pa, ra) ( ( FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_RD) )|\
113 FEC_MII_PA(pa) | FEC_MII_RA(ra) )
114 #define FEC_MII_WRITE(pa, ra, v) ( FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_WR)|\
115 FEC_MII_PA(pa) | FEC_MII_RA(ra) |FEC_MII_SET_DATA(v) )
117 #define MII_SPEED_SHIFT 1
118 #define MII_SPEED_MASK 0x0000003F
119 #define MII_SPEED(x) ( (((((x)+499999)/2500000)&(MII_SPEED_MASK))>>1)<<(MII_SPEED_SHIFT) )
121 /*the defines of MIB control */
122 #define FEC_MIB_DISABLE 0x80000000
124 /*the defines of Receive Control*/
125 #define FEC_RCR_FCE 0x00000020
126 #define FEC_RCR_BC_REJ 0x00000010
127 #define FEC_RCR_PROM 0x00000008
128 #define FEC_RCR_MII_MODE 0x00000004
130 /*the defines of Transmit Control*/
131 #define FEC_TCR_RFC_PAUSE 0x00000010
132 #define FEC_TCR_FDEN 0x00000004
134 /*the defines of buffer description*/
135 #define FEC_BD_RX_NUM 256
136 #define FEC_BD_TX_NUM 2
138 #ifdef CYGPKG_HAL_ARM_MX25
139 /*the defines for MIIGSK */
141 /* RMII frequency control: 0=50MHz, 1=5MHz */
142 #define MIIGSK_CFGR_FRCONT (1 << 6)
145 #define MIIGSK_CFGR_LBMODE (1 << 4)
148 #define MIIGSK_CFGR_EMODE (1 << 3)
150 /* MII gasket mode field */
151 #define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
153 /* MMI/7-Wire mode */
154 #define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
157 #define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
159 /* reflects MIIGSK Enable bit (RO) */
160 #define MIIGSK_ENR_READY (1 << 2)
162 /* enable MIGSK (set by default) */
163 #define MIIGSK_ENR_EN (1 << 1)
166 typedef struct mxc_fec_reg_s
169 /*0x004*/ unsigned long eir; /* Interrupt Event Register */
170 /*0x008*/ unsigned long eimr; /* Interrupt Mask Register */
172 /*0x010*/ unsigned long rdar; /* Receive Descriptor Active Register*/
173 /*0x014*/ unsigned long tdar; /* Transmit Descriptor Active Register*/
174 unsigned long res3[3];
175 /*0x024*/ unsigned long ecr; /*Receive Descriptor Active Register*/
176 unsigned long res4[6];
177 /*0x040*/ unsigned long mmfr; /*MII Management Frame Register */
178 /*0x044*/ unsigned long mscr; /*MII Speed Control Register */
179 unsigned long res5[7];
180 /*0x064*/ unsigned long mibc; /*MII Control/Status Register */
181 unsigned long res6[7];
182 /*0x084*/ unsigned long rcr; /*Receive Control Register */
183 unsigned long res7[15];
184 /*0x0C4*/ unsigned long tcr; /*Transmit Control register */
185 unsigned long res8[7];
186 /*0x0E4*/ unsigned long palr; /*Physical Address Low Register*/
187 /*0x0E8*/ unsigned long paur; /*Physical Address High+Type Register*/
188 /*0x0EC*/ unsigned long opd; /*Opcode+Pause Duration */
189 unsigned long res9[10];
190 /*0x118*/ unsigned long iaur; /*Upper 32bits Individual Hash Table*/
191 /*0x11c*/ unsigned long ialr; /*lower 32bits Individual Hash Table*/
192 /*0x120*/ unsigned long gaur; /*Upper 32bits Group Hash Table*/
193 /*0x124*/ unsigned long galr; /*lower 32bits Group Hash Table*/
194 unsigned long res10[7];
195 /*0x144*/ unsigned long tfwr; /*Trasmit FIFO Watermark */
197 /*0x14c*/ unsigned long frbr; /*FIFO Receive Bound Register*/
198 /*0x150*/ unsigned long frsr; /*FIFO Receive FIFO Start Registers*/
199 unsigned long res12[11];
200 /*0x180*/ unsigned long erdsr; /*Pointer to Receive Descriptor Ring*/
201 /*0x184*/ unsigned long etdsr; /*Pointer to Transmit Descriptor Ring*/
202 /*0x188*/ unsigned long emrbr; /*Maximum Receive Buffer size*/
203 #ifdef CYGPKG_HAL_ARM_MX25
204 unsigned long res13[93];
205 /*0x300*/ unsigned short miigsk_cfgr; /* MIIGSK Configuration Register */
206 unsigned short res14[3];
207 /*0x308*/ unsigned short miigsk_enr; /* MIIGSK Enable Register */
211 #define BD_RX_ST_EMPTY 0x8000
212 #define BD_RX_ST_WRAP 0x2000
213 #define BD_RX_ST_LAST 0x0800
214 #define BD_RX_ST_ERRS 0x0037
216 #define BD_TX_ST_RDY 0x8000
217 #define BD_TX_ST_WRAP 0x2000
218 #define BD_TX_ST_LAST 0x0800
219 #define BD_TX_ST_TC 0x0400
220 #define BD_TX_ST_ABC 0x0200
222 typedef struct mxc_fec_bd_t
224 unsigned short int length; /*packet size*/
225 unsigned short int status; /*control & statue of this buffer description*/
226 unsigned char *data; /*frame buffer address*/
229 typedef struct mxc_fec_priv_s
231 mxc_fec_reg_t *hw_reg; /*the register base address of FEC*/
232 #ifdef CYGPKG_DEVS_ETH_PHY
233 eth_phy_access_t *phy;
235 unsigned char phy_addr; /*the address of PHY which associated with FEC controller*/
237 unsigned char tx_busy; /*0:free, 1:transmitting frame*/
238 unsigned char res[2];
239 unsigned long status; /*the status of FEC device:link-status etc.*/
240 unsigned long tx_key; /*save the key delivered from send function*/
241 mxc_fec_bd_t *rx_bd; /*the receive buffer description ring*/
242 mxc_fec_bd_t *rx_cur; /*the next recveive buffer description*/
243 mxc_fec_bd_t *tx_bd; /*the transmit buffer description rign*/
244 mxc_fec_bd_t *tx_cur; /*the next transmit buffer description*/
245 cyg_bool (*provide_esa)(unsigned char *);
248 #define MXC_FEC_PRIVATE(x) ((mxc_fec_priv_t *)(x)->driver_private)
250 /*The defines of the status field of mxc_fec_priv_t */
251 #define FEC_STATUS_LINK_ON 0x80000000
252 #define FEC_STATUS_FULL_DPLX 0x40000000
253 #define FEC_STATUS_AUTO_NEG 0x20000000
254 #define FEC_STATUS_100M 0x10000000
256 /*The defines about PHY */
258 #define PHY_PORT_ADDR 0x01
260 #define PHY_PORT_ADDR FEC_PHY_ADDR
263 #define PHY_CTRL_REG 0x00
264 #define PHY_CTRL_RESET 0x8000
265 #define PHY_CTRL_AUTO_NEG 0x1000
266 #define PHY_CTRL_FULL_DPLX 0x0100
268 #define PHY_STATUS_REG 0x01
269 #define PHY_STATUS_LINK_ST 0x0004
271 #define PHY_IDENTIFY_1 0x02
272 #define PHY_IDENTIFY_2 0x03
273 #define PHY_ID1_SHIFT 2
274 #define PHY_ID1_MASK 0xFFFF
275 #define PHY_ID2_SHIFT 8
276 #define PHY_ID2_MASK 0xFC00
277 #define PHY_MODE_NUM 0x03F0
278 #define PHY_REV_NUM 0x000F
280 #define PHY_DIAG_REG 0x12
281 #define PHY_DIAG_DPLX 0x0800
282 #define PHY_DIAG_RATE 0x0400
284 #define PHY_MODE_REG 0x15
285 #define PHY_LED_SEL 0x200
287 #define PHY_AUTO_NEG_REG 0x5
288 #define PHY_AUTO_10BASET 0x20
289 #define PHY_AUTO_10BASET_DPLX 0x40
290 #define PHY_AUTO_100BASET 0x80
291 #define PHY_AUTO_100BASET_DPLX 0x100
293 #define PHY_AUTO_NEG_EXP_REG 0x6
294 #define PHY_AUTO_NEG_NEW_PAGE 0x2
295 #define PHY_AUTO_NEG_CAP 0x1
297 #define PHY_INT_SRC_REG 29
298 #define PHY_INT_AUTO_NEG 0x40
299 #define FEC_COMMON_TICK 2
300 #define FEC_COMMON_TIMEOUT (1000*1000)
301 #define FEC_MII_TICK 2
302 #define FEC_MII_TIMEOUT (1000*1000)
303 #endif // _CYGONCE_ETH_FEC_H_