1 //==========================================================================
5 // RealTek 8139 ethernet driver
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //####BSDCOPYRIGHTBEGIN####
42 // -------------------------------------------
44 // Portions of this software may have been derived from OpenBSD or
45 // other sources, and are covered by the appropriate copyright
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50 //####BSDCOPYRIGHTEND####
51 //==========================================================================
52 //#####DESCRIPTIONBEGIN####
54 // Author(s): Eric Doenges
55 // Contributors: Chris Nimmers, Gary Thomas, Andy Dyer
58 // Description: hardware driver for RealTek 8139 ethernet
59 // Notes: This is a very basic driver that will send and receive
60 // packets and not much else. A lot of features of the 8139
61 // are not supported (power management, MII interface,
62 // access to the serial eeprom, 'twister tuning', etc.).
64 // Many of the configuration options (like media type and
65 // speed) the 8139 has are taken directly from the serial
66 // eeprom and are not currently configurable from this driver.
68 // I've tentatively added some code to handle cache coherency
69 // issues for platforms that do not have a separate address
70 // space for uncached memory access and do not do cache
71 // snooping for PCI bus masters. This code can be activated by
72 // defining CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
73 // in the platform specific .inl file. Note that if
74 // CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY is
75 // defined, the .inl file is also responsible for making sure
76 // the receive and transmit buffers are located in memory in
77 // such a way that flushing or invalidating cache lines for
78 // these buffers will not affect any other buffers. See the
79 // README in the doc directory for some suggestions on how
82 // Since the official data sheet for this chip is a bit
83 // vague, I had to look at the Linux and OpenBSD drivers to
84 // understand the basic workings of the chip; however, I have
85 // not copied any code from those drivers to avoid tainting
90 //####DESCRIPTIONEND####
92 //==========================================================================
93 #include <pkgconf/system.h>
94 #ifdef CYGPKG_IO_ETH_DRIVERS
95 #include <pkgconf/io_eth_drivers.h>
97 #include <pkgconf/devs_eth_rltk_8139.h>
99 #include <cyg/infra/cyg_type.h>
100 #include <cyg/infra/cyg_ass.h>
101 #include <cyg/infra/diag.h>
102 #include <cyg/hal/hal_arch.h>
103 #include <cyg/hal/drv_api.h>
104 #include <cyg/hal/hal_cache.h>
105 #include <cyg/io/eth/netdev.h>
106 #include <cyg/io/eth/eth_drv.h>
108 #include <string.h> /* for memset */
111 #include <cyg/io/pci.h>
113 #error "This driver requires the PCI package (CYGPKG_IO_PCI)"
116 #include <cyg/io/pci.h>
118 /* Necessary for memory mapping macros */
119 #include CYGHWR_MEMORY_LAYOUT_H
121 /* Check if we should be dumping debug information or not */
122 #if defined CYGDBG_DEVS_ETH_RLTK_8139_CHATTER \
123 && (CYGDBG_DEVS_ETH_RLTK_8139_CHATTER > 0)
124 #define DEBUG_RLTK8139_DRIVER
129 /* Which interrupts we will handle */
130 #define RLTK8139_IRQ (IR_SERR|IR_FOVW|IR_RXOVW|IR_TER|IR_TOK|IR_RER|IR_ROK|IR_FUN)
132 /* Allow platform-specific configuration of the driver */
133 #ifndef CYGDAT_DEVS_ETH_RLTK_8139_INL
134 #error "CYGDAT_DEVS_ETH_RLTK_8139_INL not defined"
136 #include CYGDAT_DEVS_ETH_RLTK_8139_INL
139 #ifndef CYGHWR_RLTK_8139_PLF_INIT
140 #define CYGHWR_RLTK_8139_PLF_INIT(sc) do {} while(0)
144 * If software cache coherency is required, the HAL_DCACHE_INVALIDATE
145 * hal macro must be defined as well.
147 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
148 #if !defined HAL_DCACHE_INVALIDATE || !defined HAL_DCACHE_FLUSH
149 #error "HAL_DCACHE_INVALIDATE/HAL_DCACHE_FLUSH not defined for this platform but CYGPKG_DEVS_ETH_RLTK_8139_CACHE_COHERENCY was defined."
153 /* Local driver function declarations */
154 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
155 static cyg_uint32 rltk8139_isr(cyg_vector_t vector, cyg_addrword_t data);
158 #ifdef ETH_DRV_SET_MC_LIST
159 static cyg_uint32 ether_crc(cyg_uint8 *data, int length);
160 static void rltk8139_set_multicast_list(Rltk8139_t *rltk8139_info,
161 struct eth_drv_mc_list *mc_list);
164 static void rltk8139_reset(struct eth_drv_sc *sc);
165 static bool rltk8139_init(struct cyg_netdevtab_entry *tab);
166 static void rltk8139_start(struct eth_drv_sc *sc, unsigned char *enaddr,
168 static void rltk8139_stop(struct eth_drv_sc *sc);
169 static int rltk8139_control(struct eth_drv_sc *sc, unsigned long key,
170 void *data, int data_length);
171 static int rltk8139_can_send(struct eth_drv_sc *sc);
172 static void rltk8139_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
173 int sg_len, int total_len, unsigned long key);
174 static void rltk8139_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
176 static void rltk8139_deliver(struct eth_drv_sc *sc);
177 static void rltk8139_poll(struct eth_drv_sc *sc);
178 static int rltk8139_int_vector(struct eth_drv_sc *sc);
180 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
181 static cyg_uint16 rltk8139_eeprom_read( char *cpErAddr, cyg_uint8 Cmd, cyg_uint8 RomAdr );
182 static void rltk8139_eeprom_write( char *cpErAddr, cyg_uint8 Cmd, cyg_uint8 RomAdr, cyg_uint16 SrcData );
185 #ifdef DEBUG_RLTK8139_DRIVER
186 void rltk8139_print_state(struct eth_drv_sc *sc);
189 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
190 #define EEPROM_CMD_READ 0x06 // eeprom read command
191 #define EEPROM_CMD_WRITE 0x05 // eeprom write command
192 #define EEPROM_PG_ON 0x80
193 #define EEPROM_PG_EECS 0x08
194 #define EEPROM_PG_EESK 0x04
195 #define EEPROM_PG_EEDI 0x02
196 #define EEPROM_PG_EEDO 0x01
197 #define EEPROM_WR_BUSY_RETRIES 100 // ready wait re-try count
199 #define EEPROM_MASK(_param0_,_param1_) ((_param0_ & _param1_) ? EEPROM_PG_EEDI : 0 )
202 #define EEPROM_WR_DATA(_addr_,_txdata_) HAL_WRITE_UINT8(_addr_,_txdata_);
204 #define EEPROM_WR_DATAPULSE(_addr_,_txdata_) HAL_WRITE_UINT8(_addr_,_txdata_); \
205 cyg_thread_delay(0); \
206 HAL_WRITE_UINT8(_addr_,_txdata_ | EEPROM_PG_EESK);
208 #define EEPROM_RD_DATA(_addr_,_txdata_,_rxdata_) { \
209 cyg_uint16 read_data; \
210 HAL_WRITE_UINT8(_addr_,_txdata_); \
211 cyg_thread_delay(1); \
212 HAL_READ_UINT8(_addr_, read_data); \
214 _rxdata_ |= ((read_data & EEPROM_PG_EEDO) ? 0x0001 : 0x0000 ); \
215 HAL_WRITE_UINT8(_addr_,_txdata_ | EEPROM_PG_EESK); }
219 * Define inline functions to access the card. This will also handle
220 * endianess issues in one place. This code was lifted from the eCos
223 #if (CYG_BYTEORDER == CYG_MSBFIRST)
224 #define HAL_CTOLE32(x) ((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | (((x) >> 24) & 0xff))
225 #define HAL_LE32TOC(x) ((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | (((x) >> 24) & 0xff))
227 #define HAL_CTOLE16(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
228 #define HAL_LE16TOC(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
231 OUTB(cyg_uint8 value,
232 cyg_uint32 io_address)
234 HAL_WRITE_UINT8( io_address, value);
238 OUTW(cyg_uint16 value, cyg_uint32 io_address)
240 HAL_WRITE_UINT16(io_address,
241 (((value & 0xff) << 8) | ((value & 0xff00) >> 8)) );
245 OUTL(cyg_uint32 value, cyg_uint32 io_address)
247 HAL_WRITE_UINT32(io_address,
248 ((((value) & 0xff) << 24) | (((value) & 0xff00) << 8)
249 | (((value) & 0xff0000) >> 8)
250 | (((value) >> 24) & 0xff)) );
253 static inline cyg_uint8
254 INB(cyg_uint32 io_address)
257 HAL_READ_UINT8(io_address, d);
261 static inline cyg_uint16
262 INW(cyg_uint32 io_address)
265 HAL_READ_UINT16( io_address, d );
266 return (((d & 0xff) << 8) | ((d & 0xff00) >> 8));
269 static inline cyg_uint32
270 INL(cyg_uint32 io_address)
273 HAL_READ_UINT32(io_address, d);
274 return ((((d) & 0xff) << 24) | (((d) & 0xff00) << 8)
275 | (((d) & 0xff0000) >> 8) | (((d) >> 24) & 0xff));
279 // Maintaining the same styleee as above...
280 #define HAL_CTOLE32(x) ((((x))))
281 #define HAL_LE32TOC(x) ((((x))))
283 #define HAL_CTOLE16(x) ((((x))))
284 #define HAL_LE16TOC(x) ((((x))))
286 static inline void OUTB(cyg_uint8 value, cyg_uint32 io_address)
287 { HAL_WRITE_UINT8( io_address, value ); }
289 static inline void OUTW(cyg_uint16 value, cyg_uint32 io_address)
290 { HAL_WRITE_UINT16( io_address, value ); }
292 static inline void OUTL(cyg_uint32 value, cyg_uint32 io_address)
293 { HAL_WRITE_UINT32( io_address, value ); }
295 static inline cyg_uint8 INB(cyg_uint32 io_address)
296 { cyg_uint8 _t_; HAL_READ_UINT8( io_address, _t_ ); return _t_; }
298 static inline cyg_uint16 INW(cyg_uint32 io_address)
299 { cyg_uint16 _t_; HAL_READ_UINT16( io_address, _t_ ); return _t_; }
301 static inline cyg_uint32 INL(cyg_uint32 io_address)
302 { cyg_uint32 _t_; HAL_READ_UINT32( io_address, _t_ ); return _t_; }
308 * Table of all known PCI device/vendor ID combinations for the RealTek 8139.
309 * Add them as you get to know them.
311 #define CYGNUM_DEVS_ETH_RLTK_8139_KNOWN_ALIASES 3
312 static pci_identifier_t
313 known_8139_aliases[CYGNUM_DEVS_ETH_RLTK_8139_KNOWN_ALIASES] = {
314 { 0x10ec, 0x8139, NULL }, /* This is the official RealTek vendor/device code of 8139D(L) */
315 { 0x11db, 0x1234, NULL}, /* SEGA DreamCast BroadBandAdapter */
316 { 0x10ec, 0x8129, NULL } /* This is the official RealTek vendor/device code of 8139C(L) */
321 * Check if the device description matches a known 8139 alias.
324 rltk8139_find_match_func(cyg_uint16 vendor_id, cyg_uint16 device_id,
325 cyg_uint32 class_id, void *p)
330 for (i = 0; i < CYGNUM_DEVS_ETH_RLTK_8139_KNOWN_ALIASES; ++i) {
331 if (((known_8139_aliases[i].vendor_id == PCI_ANY_ID) ||
332 (known_8139_aliases[i].vendor_id == vendor_id)) &&
333 ((known_8139_aliases[i].device_id == PCI_ANY_ID) ||
334 (known_8139_aliases[i].device_id == device_id)))
343 * Find the Nth 8139 device on all attached PCI busses and do some initial
344 * PCI-type initialization. Also setup the interrupt for use in eCos.
347 rltk8139_find(int n_th, struct eth_drv_sc *sc)
349 Rltk8139_t *rltk8139_info;
350 cyg_pci_device_id pci_device_id;
351 cyg_pci_device pci_device_info;
356 /* Go through all PCI devices until we find the Nth 8139 chip */
357 pci_device_id = CYG_PCI_NULL_DEVID;
359 if (!cyg_pci_find_matching(&rltk8139_find_match_func, NULL,
364 } while (found != n_th);
366 /* Save device ID in driver private data in case we ever need it again */
367 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
368 rltk8139_info->pci_device_id = pci_device_id;
370 /* Now that we have found the device, we can extract some data about it */
371 cyg_pci_get_device_info(pci_device_id, &pci_device_info);
373 /* Get the assigned interrupt and set up ISR and DSR for it. */
374 if (cyg_pci_translate_interrupt(&pci_device_info, &rltk8139_info->vector)) {
375 #ifdef DEBUG_RLTK8139_DRIVER
376 diag_printf(" Wired to HAL interrupt vector %d\n", rltk8139_info->vector);
379 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
381 * Note that we use the generic eth_drv_dsr routine instead of
384 cyg_drv_interrupt_create(rltk8139_info->vector,
385 rltk8139_info->isr_priority,
389 &rltk8139_info->interrupt_handle,
390 &rltk8139_info->interrupt);
391 cyg_drv_interrupt_attach(rltk8139_info->interrupt_handle);
395 #ifdef DEBUG_RLTK8139_DRIVER
396 diag_printf(" Does not generate interrupts.\n");
401 * Call 'cyg_pci_configure_device' for those platforms that do not
402 * configure the PCI bus during HAL initialization. According to Nick
403 * Garnett, there are good reasons to not configure PCI devices during HAL
404 * initialization. Also according to Nick, calling
405 * 'cyg_pci_configure_device' for devices already configured should have no
406 * effect and thus is safe to do.
408 if (cyg_pci_configure_device(&pci_device_info)) {
409 #ifdef DEBUG_RLTK8139_DRIVER
411 diag_printf("Found device #%d on bus %d, devfn 0x%02x:\n", n_th,
412 CYG_PCI_DEV_GET_BUS(pci_device_id),
413 CYG_PCI_DEV_GET_DEVFN(pci_device_id));
415 if (pci_device_info.command & CYG_PCI_CFG_COMMAND_ACTIVE)
416 diag_printf(" Note that board is active. Probed"
417 " sizes and CPU addresses are invalid!\n");
419 diag_printf(" Vendor 0x%04x", pci_device_info.vendor);
420 diag_printf("\n Device 0x%04x", pci_device_info.device);
421 diag_printf("\n Command 0x%04x, Status 0x%04x\n",
422 pci_device_info.command, pci_device_info.status)
425 diag_printf(" Class/Rev 0x%08x", pci_device_info.class_rev);
426 diag_printf("\n Header 0x%02x\n", pci_device_info.header_type);
428 diag_printf(" SubVendor 0x%04x, Sub ID 0x%04x\n",
429 pci_device_info.header.normal.sub_vendor,
430 pci_device_info.header.normal.sub_id);
432 for(i = 0; i < CYG_PCI_MAX_BAR; i++) {
433 diag_printf(" BAR[%d] 0x%08x /", i, pci_device_info.base_address[i]);
434 diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
435 pci_device_info.base_size[i], pci_device_info.base_map[i]);
440 #ifdef DEBUG_RLTK8139_DRIVER
441 diag_printf("Failed to configure 8139 device #%d\n", n_th);
447 * Enable memory mapped and port based I/O and busmastering. We currently
448 * only support IO space accesses; memory mapping is enabled so that bit
449 * DVRLOAD in CONFIG1 is cleared automatically.
451 * NOTE: it seems that for some configurations/HALs, the device is already
452 * activated at this point, even though eCos' documentation suggests
453 * it shouldn't be. At least in my case, this is not a problem.
455 cyg_pci_read_config_uint16(pci_device_info.devid, CYG_PCI_CFG_COMMAND,
457 command |= (CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MEMORY
458 | CYG_PCI_CFG_COMMAND_MASTER);
459 cyg_pci_write_config_uint16(pci_device_info.devid, CYG_PCI_CFG_COMMAND,
463 * This is the base address used to talk to the device. The 8139's IOAR
464 * and MEMAR registers are BAR0 and BAR1, respectively.
466 rltk8139_info->base_address = pci_device_info.base_map[0];
469 * Read the MAC address. The RealTek data sheet seems to claim this should
470 * only be read in 4 byte accesses, but the code below works just fine.
472 for (found = 0; found < 6; ++found)
473 rltk8139_info->mac[found] = INB(rltk8139_info->base_address + IDR0 + found);
476 * This is the indicator for "uses an interrupt". The code was lifted
477 * from the eCos Intel 82559 driver.
479 if (rltk8139_info->interrupt_handle != 0) {
480 cyg_drv_interrupt_acknowledge(rltk8139_info->vector);
482 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
483 cyg_drv_interrupt_unmask(rltk8139_info->vector);
490 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
492 * Interrupt service routine. We do not clear the interrupt status bits
493 * (since this should really only be done after handling whatever caused
494 * the interrupt, and that is done in the '_deliver' routine), but instead
495 * clear the interrupt mask.
497 * If we are sharing interrupts with other devices, we have two options
500 * 1. Mask the interrupt vector completly. Personally I think this is a bad
501 * idea because the other devices sharing this interrupt are also masked
502 * until the network thread gets around to calling the '_deliver' routine.
504 * 2. Use the interrupt mask register in the 8139 to mask just the interrupt
505 * request coming from the 8139. This way, the other devices' requests
506 * can still be serviced.
509 rltk8139_isr(cyg_vector_t vector, cyg_addrword_t data)
511 Rltk8139_t *rltk8139_info;
512 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SHARE_INTERRUPTS
516 rltk8139_info = (Rltk8139_t *)(((struct eth_drv_sc *)data)->driver_private);
518 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SHARE_INTERRUPTS
520 * If interrupt sharing is enabled, check if the interrupt is really
521 * intended for us. Note that while the RealTek data sheet claims that
522 * reading the interrupt status register will clear all it's bits,
523 * this is not true, so we can read it without problems.
525 if (!(isr = INW(rltk8139_info->base_address + ISR)))
529 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_MASK_INTERRUPTS_IN_8139
530 /* Clear the interrupt mask to stop the current request. */
531 OUTW(0, rltk8139_info->base_address + IMR);
533 /* Mask the interrupt */
534 cyg_interrupt_mask(vector);
537 /* Acknowledge the interrupt for those platforms were this is necessary */
538 cyg_interrupt_acknowledge(vector);
540 return (CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
542 #endif /* ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE */
545 * Reset the chip. This function is not exported to higher level software.
548 rltk8139_reset(struct eth_drv_sc *sc)
551 rltk8139_start(sc, NULL, 0);
554 #ifdef ETH_DRV_SET_MC_LIST
556 * I assume (hope !) that this is identical to Ethernet's CRC algorithm
557 * specified in IEEE 802.3. It does seem to calculate the same CRC that
558 * the 8139 itself does, so I think it is correct.
559 * Note that while Ethernet's polynomial is usually specified as 04C11DB7,
560 * we must use EDB88320 because we shift the bits to the left, not the right.
561 * (See ftp://ftp.rocksoft.com/papers/crc_v3.txt for a good description of
565 ether_crc(cyg_uint8 *data, int length)
568 cyg_uint32 crc = 0xFFFFFFFFU;
570 while (length-- > 0) {
572 for (bit = 0; bit < 8; ++bit) {
574 crc = (crc >> 1) ^ 0xEDB88320U;
580 return crc ^ 0xFFFFFFFFU;
585 * Set up multicast filtering. The way I understand existing driver code
586 * (Linux and OpenBSD), the 8139 calculates the ethernet CRC of
587 * incoming addresses and uses the top 6 bits as an index into a hash
588 * table. If the corresponding bit is set in MAR0..7, the address is
592 rltk8139_set_multicast_list(Rltk8139_t *rltk8139_info,
593 struct eth_drv_mc_list *mc_list)
595 cyg_uint32 mar[2], hash;
598 /* If 'mc_list' is NULL, accept all multicast packets. */
600 mar[0] = 0xFFFFFFFFU;
601 mar[1] = 0xFFFFFFFFU;
607 for (i = 0; i < mc_list->len; ++i) {
608 hash = ether_crc(&mc_list->addrs[i][0], ETHER_ADDR_LEN) >> 26;
609 mar[hash >> 5] |= (1 << (hash & 0x1F));
613 /* Program the new filter values */
614 OUTL(mar[0], rltk8139_info->base_address + MAR0);
615 OUTL(mar[1], rltk8139_info->base_address + MAR4);
617 #endif /* ifdef ETH_DRV_SET_MC_LIST */
621 * Initialize the network interface. Since the chips is reset by calling
622 * _stop() and _start(), any code that will never need to be executed more
623 * than once after system startup should go here.
626 rltk8139_init(struct cyg_netdevtab_entry *tab)
628 struct eth_drv_sc *sc;
629 Rltk8139_t *rltk8139_info;
632 sc = (struct eth_drv_sc *)(tab->device_instance);
633 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
636 * Initialize the eCos PCI library. According to the documentation, it
637 * is safe to call this function multiple times, so we call it just to
638 * be sure it has been done.
643 * Scan the PCI bus for the specified chip. The '_find' function will also
644 * do some basic PCI initialization.
646 if (!rltk8139_find(rltk8139_info->device_num, sc)) {
647 #ifdef DEBUG_RLTK8139_DRIVER
648 diag_printf("rltk8139_init: could not find RealTek 8139 chip #%d.\n",
649 rltk8139_info->device_num);
654 /* platform depends initialize */
655 CYGHWR_RLTK_8139_PLF_INIT(sc);
658 * The initial tx threshold is set here to prevent it from being reset
659 * with every _start().
661 rltk8139_info->tx_threshold = 3;
663 /* Initialize upper level driver */
664 (sc->funs->eth_drv->init)(sc, rltk8139_info->mac);
671 * (Re)Start the chip, initializing data structures and enabling the
672 * transmitter and receiver. Currently, 'flags' is unused by eCos.
675 rltk8139_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
677 Rltk8139_t *rltk8139_info;
681 #ifdef DEBUG_RLTK8139_DRIVER
682 diag_printf("rltk8139_start(%s)\n", sc->dev_name);
685 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
688 * Reset the chip. Existing driver code implies that this may take up
689 * to 10ms; since I don't know under what exact circumstances this code may
690 * be called I busy wait here regardless.
692 OUTB(RST, rltk8139_info->base_address + CR);
693 while (INB(rltk8139_info->base_address + CR) & RST);
695 #ifdef DEBUG_RLTK8139_DRIVER
696 diag_printf("rltk8139_start(%s): 8139 was successfully reset.\n",
701 * Clear the key storage area. These keys are used by the eCos networking
702 * support code to keep track of individual packets.
704 for (i = 0; i < NUM_TX_DESC; ++i)
705 rltk8139_info->tx_desc_key[i] = 0;
707 /* Initialize transmission buffer control */
708 rltk8139_info->tx_free_desc = 0;
709 rltk8139_info->tx_num_free_desc = NUM_TX_DESC;
712 * Set the requested MAC address if enaddr != NULL. This is a special
713 * feature of my '_start' function since it's used to reset the chip after
716 if (enaddr != NULL) {
717 for (i = 0; i < 6; ++i) {
718 rltk8139_info->mac[i] = enaddr[i];
719 OUTB(enaddr[i], rltk8139_info->base_address + IDR0 + i);
724 * Now setup the transmission and reception buffers. These could be done
725 * in _init() and kept around, but putting them here fits better logically.
727 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)(rltk8139_info->tx_buffer
729 rltk8139_info->base_address + TSAD0);
730 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)(rltk8139_info->tx_buffer
732 rltk8139_info->base_address + TSAD1);
733 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)(rltk8139_info->tx_buffer
735 rltk8139_info->base_address + TSAD2);
736 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)(rltk8139_info->tx_buffer
738 rltk8139_info->base_address + TSAD3);
739 OUTL(CYGARC_PCI_DMA_ADDRESS((cyg_uint32)rltk8139_info->rx_ring),
740 rltk8139_info->base_address + RBSTART);
743 * Enable the transmitter and receiver, then clear the missed packet
746 OUTB(INB(rltk8139_info->base_address + CR) | (TE|RE),
747 rltk8139_info->base_address + CR);
748 OUTL(0, rltk8139_info->base_address + MPC);
751 * It seems the receiver and transmitter configuration can only
752 * be set after the transmitter/receiver have been enabled.
754 OUTL(TXCFG, rltk8139_info->base_address + TCR);
755 OUTL(RXCFG | AM, rltk8139_info->base_address + RCR);
758 * Enable the transmitter and receiver again. I'm not sure why this is
759 * necessary; the Linux driver does it so we do it here just to be on
762 OUTB(INB(rltk8139_info->base_address + CR) | (TE|RE),
763 rltk8139_info->base_address + CR);
765 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
767 * If this driver was not compiled in stand alone (without interrupts)
768 * mode, enable interrupts.
770 OUTW(RLTK8139_IRQ, rltk8139_info->base_address + IMR);
773 #ifdef DEBUG_RLTK8139_DRIVER
774 rltk8139_print_state(sc);
780 * Stop the chip, disabling the transmitter and receiver.
783 rltk8139_stop(struct eth_drv_sc *sc)
785 Rltk8139_t *rltk8139_info;
788 #ifdef DEBUG_RLTK8139_DRIVER
789 diag_printf("rltk8139_stop(%s)\n", sc->dev_name);
792 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
794 /* Disable receiver and transmitter */
795 OUTB(INB(rltk8139_info->base_address + CR) & ~(TE|RE),
796 rltk8139_info->base_address + CR);
798 /* Mask all interrupts */
799 OUTW(0, rltk8139_info->base_address + IMR);
804 * 8139 control function. Unlike a 'real' ioctl function, this function is
805 * not required to tell the caller why a request failed, only that it did
806 * (see the eCos documentation).
809 rltk8139_control(struct eth_drv_sc *sc, unsigned long key, void *data,
813 Rltk8139_t *rltk8139_info;
815 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
816 cyg_uint16 WrData, RdData;
821 #ifdef DEBUG_RLTK8139_DRIVER
822 diag_printf("rltk8139_control(%08x, %lx)\n", sc, key);
825 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
828 #ifdef ETH_DRV_SET_MAC_ADDRESS
829 case ETH_DRV_SET_MAC_ADDRESS:
830 if ( 6 != data_length )
833 /* Set the mac address */
834 for (i = 0; i < 6; ++i) {
835 rltk8139_info->mac[i] = *(((cyg_uint8 *)data) + i);
836 OUTB(rltk8139_info->mac[i], rltk8139_info->base_address + IDR0 + i);
839 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
840 pSrcData = (cyg_uint8 *)data;
841 for(i = 0; i < 3; i++){
842 WrData = ((cyg_uint16)(*pSrcData++)) & 0xff;
843 WrData |= ((cyg_uint16)(*pSrcData++)) << 8;
844 for( iRetry = 0; iRetry < 3; iRetry++){
845 rltk8139_eeprom_write(
846 (char *)(rltk8139_info->base_address + CR9346),
847 EEPROM_CMD_WRITE, i + 7, WrData);
848 RdData = rltk8139_eeprom_read(
849 (char *)(rltk8139_info->base_address + CR9346),
850 EEPROM_CMD_READ, i + 7);
851 if( RdData == WrData ){
861 #ifdef ETH_DRV_GET_MAC_ADDRESS
862 case ETH_DRV_GET_MAC_ADDRESS:
863 if (6 != data_length)
866 memcpy(data, rltk8139_info->mac, 6);
870 #ifdef ETH_DRV_GET_IF_STATS_UD
871 case ETH_DRV_GET_IF_STATS_UD: // UD == UPDATE
872 //ETH_STATS_INIT( sc ); // so UPDATE the statistics structure
875 #ifdef ETH_DRV_GET_IF_STATS
876 case ETH_DRV_GET_IF_STATS:
878 #if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
882 #ifdef ETH_DRV_SET_MC_LIST
883 case ETH_DRV_SET_MC_LIST:
885 * Program the 8139's multicast filter register. If the eth_drv_mc_list
886 * contains at least one element, set the accept multicast bit in the
887 * receive config register.
889 rltk8139_set_multicast_list(rltk8139_info, (struct eth_drv_mc_list *)data);
890 if (((struct eth_drv_mc_list *)data)->len > 0)
891 OUTL(INL(rltk8139_info->base_address + RCR) | AM,
892 rltk8139_info->base_address + RCR);
894 OUTL(INL(rltk8139_info->base_address + RCR) & ~AM,
895 rltk8139_info->base_address + RCR);
898 #endif // ETH_DRV_SET_MC_LIST
900 #ifdef ETH_DRV_SET_MC_ALL
901 case ETH_DRV_SET_MC_ALL:
903 * Set the accept multicast bit in the receive config register and
904 * program the multicast filter to accept all addresses.
906 rltk8139_set_multicast_list(rltk8139_info, NULL);
907 OUTL(INL(rltk8139_info->base_address + RCR) | AM,
908 rltk8139_info->base_address + RCR);
910 #endif // ETH_DRV_SET_MC_ALL
921 * Check if a new packet can be sent.
924 rltk8139_can_send(struct eth_drv_sc *sc)
926 return ((Rltk8139_t *)(sc->driver_private))->tx_num_free_desc;
931 * Send a packet over the wire.
934 rltk8139_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
935 int total_len, unsigned long key)
937 Rltk8139_t *rltk8139_info;
938 cyg_uint8 *tx_buffer;
939 struct eth_drv_sg *last_sg;
942 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
944 #ifdef DEBUG_RLTK8139_DRIVER
945 diag_printf("rltk8139_send(%s, %08x, %d, %d, %08lx)\n",
946 sc->dev_name, sg_list, sg_len, total_len, key);
949 CYG_ASSERT(total_len <= TX_BUF_SIZE, "packet too long");
952 * Get the next free descriptor to send. We lock out all interrupts
953 * and scheduling because we really, really do not want to be interrupted
956 * IMPORTANT NOTE: the RealTek data sheet does not really make this clear,
957 * but when they talk about a 'ring' of transmit descriptors, they
958 * _really_ mean it, i.e. you _must_ use descriptor #1 after descriptor
959 * #0 even if transmission of descriptor #0 has already completed.
964 * Sanity check to see if '_send' was called even though there is no free
965 * descriptor. This is probably unnecessary.
967 if (rltk8139_info->tx_num_free_desc == 0) {
968 cyg_drv_isr_unlock();
969 #ifdef DEBUG_RLTK8139_DRIVER
970 diag_printf("rltk8139_send(%s): no free descriptor available\n",
977 * Get the free descriptor and advance the descriptor counter modulo
978 * TX_NUM_DESC. We assume that TX_NUM_DESC will always be a power of 2.
980 desc = rltk8139_info->tx_free_desc;
981 rltk8139_info->tx_free_desc = (rltk8139_info->tx_free_desc + 1)
984 /* Decrement the number of free descriptors */
985 rltk8139_info->tx_num_free_desc -= 1;
987 /* Reenable interrupts at this point */
988 cyg_drv_isr_unlock();
991 * Determine the buffer memory to use and tell the hardware about it.
992 * Since we use fixed buffer addresses, we do not need to set up TSADx.
993 * Memorize the key so we can call the tx_done callback correctly.
995 * While it would be possible to set TSADx to the packet directly if
996 * it is stored in a linear memory area with 32 bit alignment, it seems
997 * this happens so seldomly that it's simply not worth the extra
1000 tx_buffer = (cyg_uint8 *)CYGARC_UNCACHED_ADDRESS(rltk8139_info->tx_buffer
1001 + TX_BUF_SIZE * desc);
1002 rltk8139_info->tx_desc_key[desc] = key;
1005 * Copy the data to the designated position. Note that unlike the eCos
1006 * Intel 82559 driver, we simply assume that all the scatter/gather list
1007 * elements' lengths will add up to total_len exactly, and don't check
1010 for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
1011 memcpy(tx_buffer, (void *)(sg_list->buf), sg_list->len);
1012 tx_buffer += sg_list->len;
1016 * Make sure the packet has the minimum ethernet packet size, padding
1017 * with zeros if necessary.
1019 if (total_len < MIN_ETH_FRAME_SIZE) {
1020 memset(tx_buffer, 0, MIN_ETH_FRAME_SIZE - total_len);
1021 total_len = MIN_ETH_FRAME_SIZE;
1025 * Flush the data cache here if necessary. This ensures the 8139 can
1026 * read the correct data from the transmit buffer.
1028 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
1029 HAL_DCACHE_FLUSH(rltk8139_info->tx_buffer + TX_BUF_SIZE * desc, total_len);
1033 * Now setup the correct transmit descriptor to actually send the data.
1034 * The early TX threshold is incremented by the driver until we reach a
1035 * size that prevents transmit underruns. (An earlier attempt to calculate
1036 * this parameter from the packet size didn't work).
1038 OUTL((rltk8139_info->tx_threshold << ERTXTH_SHIFT) | (total_len & SIZE),
1039 rltk8139_info->base_address + TSD0 + (desc<<2));
1044 * This routine actually retrieves data from the receive ring by
1045 * copying it into the specified scatter/gather buffers. Again,
1046 * we assume the scatter/gather list is OK and don't check against
1050 rltk8139_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list,
1053 Rltk8139_t *rltk8139_info;
1054 struct eth_drv_sg *last_sg;
1055 cyg_uint8 *rx_buffer;
1058 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
1059 rx_buffer = rltk8139_info->rx_current;
1062 * Invalidate the cache line(s) mapped to the receive buffer
1065 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
1066 HAL_DCACHE_INVALIDATE(rx_buffer, rltk8139_info->rx_size);
1069 for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
1070 if (sg_list->buf != (CYG_ADDRESS)0) {
1071 memcpy((void *)(sg_list->buf), rx_buffer, sg_list->len);
1072 rx_buffer += sg_list->len;
1079 * This function does all the heavy lifting associated with interrupts.
1082 rltk8139_deliver(struct eth_drv_sc *sc)
1084 Rltk8139_t *rltk8139_info;
1085 cyg_uint16 status, pci_status;
1090 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
1093 * The RealTek data sheet claims that reading the ISR will clear
1094 * it. This is incorrect; to clear a bit in the ISR, a '1' must be
1095 * written to the ISR instead. We immediately clear the interrupt
1096 * bits at this point.
1098 status = INW(rltk8139_info->base_address + ISR);
1099 OUTW(status, rltk8139_info->base_address + ISR);
1101 #ifdef DEBUG_RLTK8139_DRIVER
1102 diag_printf("rltk8139_deliver(%s): %04x\n", sc->dev_name, status);
1106 * Check for a PCI error. This seems like a very serious error to
1107 * me, so we will reset the chip and hope for the best.
1109 if (status & IR_SERR) {
1110 cyg_pci_read_config_uint16(rltk8139_info->pci_device_id,
1111 CYG_PCI_CFG_STATUS, &pci_status);
1112 cyg_pci_write_config_uint16(rltk8139_info->pci_device_id,
1113 CYG_PCI_CFG_STATUS, pci_status);
1114 #ifdef DEBUG_RLTK8139_DRIVER
1115 diag_printf("rltk8139_deliver(%s): PCI error %04x\n",
1116 sc->dev_name, pci_status);
1123 /* Check for transmission complete (with errors or not) */
1124 if ((status & IR_TER) || (status & IR_TOK)) {
1126 * Figure out which descriptors' status must be checked. We lock out
1127 * interrupts while manipulating the descriptor list because we do not
1128 * want to be interrupted at this point.
1133 /* Check if all descriptors are ready, in which case we are done. */
1134 if (rltk8139_info->tx_num_free_desc >= NUM_TX_DESC) {
1135 cyg_drv_isr_unlock();
1139 desc = (rltk8139_info->tx_free_desc
1140 - (NUM_TX_DESC - rltk8139_info->tx_num_free_desc))
1141 & (NUM_TX_DESC - 1);
1142 cyg_drv_isr_unlock();
1144 /* Get the current status of the descriptor */
1145 tsd = INL(rltk8139_info->base_address + TSD0 + (desc<<2));
1148 * If a transmit FIFO underrun occurred, increment the threshold
1151 if ((tsd & TUN) && (rltk8139_info->tx_threshold < 64))
1152 rltk8139_info->tx_threshold += 1;
1155 * Check if a transmission completed OK. RealTek's data sheet implies
1156 * that a successful transmission that experiences underrun will only
1157 * set TUN. This is not true; TOK is set for all successful
1161 (sc->funs->eth_drv->tx_done)(sc, rltk8139_info->tx_desc_key[desc], 0);
1163 else if (tsd & TABT) {
1165 * Set the CLRABT bit in TCR. Since I haven't encountered any
1166 * transmission aborts so far, I don't really know if this code
1169 OUTL(INL(rltk8139_info->base_address + TCR) & CLRABT,
1170 rltk8139_info->base_address + TCR);
1171 (sc->funs->eth_drv->tx_done)(sc, rltk8139_info->tx_desc_key[desc], -1);
1175 * This descriptor is not ready. Since the descriptors are used
1176 * in a ring, this means that no more descriptors are ready.
1182 * Clear the saved key value. This is not really necessary, since
1183 * the key value is never used to determine if a descriptor is
1184 * valid or not. However, clearing it is a tidier IMO.
1186 rltk8139_info->tx_desc_key[desc] = 0;
1189 * Increment the free descriptor count and go through the loop again
1190 * to see if more descriptors are ready.
1193 rltk8139_info->tx_num_free_desc += 1;
1194 cyg_drv_isr_unlock();
1198 if (status & IR_ROK) {
1200 * Received a frame. Note that '_deliver' does not actually copy any
1201 * data; it just determines how many bytes are available and tells
1202 * the generic ethernet driver about it, which then calls into
1203 * the '_recv' function to copy the data.
1206 cyg_uint32 header, length;
1209 * CAPR contains the index into the receive buffer. It is controlled
1210 * completely in software. For some reason, CAPR points 16 bytes
1211 * before the actual start of the packet.
1213 rx_pos = (INW(rltk8139_info->base_address + CAPR) + 16) % RX_BUF_LEN;
1216 * Loop until the rx buffer is empty. I have no idea how the 8139
1217 * determines if the buffer still contains a packet; it may check
1218 * that CAPR points 16 bytes before CBR.
1220 while (!(INB(rltk8139_info->base_address + CR) & BUFE)) {
1222 * Invalidate the data cache for the cache line containing the header
1225 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_SOFTWARE_CACHE_COHERENCY
1226 HAL_DCACHE_INVALIDATE(&rltk8139_info->rx_ring[rx_pos],
1227 sizeof(cyg_uint32));
1231 * The 8139 prepends each packet with a 32 bit packet header that
1232 * contains a 16 bit length and 16 bit status field, in little-endian
1235 header = HAL_LE32TOC(*((volatile cyg_uint32 *)CYGARC_UNCACHED_ADDRESS(&rltk8139_info->rx_ring[rx_pos])));
1238 * If the 8139 is still copying data for this packet into the
1239 * receive ring, it will set packet length to 0xfff0. This shouldn't
1240 * ever happen because we do not use early receive.
1242 if ((header >> 16) == 0xFFF0)
1246 * Since the 8139 appends the ethernet CRC to every packet, we
1247 * must subtract 4 from the length to get the true packet length.
1249 length = (header >> 16) - 4;
1252 * Check if the packet was received correctly. The OpenBSD driver
1253 * resets the chip if this is not the case; we attempt to salvage
1254 * following packets by doing nothing.
1256 if (!(header & HDR_ROK)) {
1260 * Packet was received OK. Determine from where to start copying
1261 * bytes. This is saved in the driver private area so rlt8139_recv
1262 * doesn't have to redetermine this information. Then, inform
1263 * the generic ethernet driver about the packet.
1265 rltk8139_info->rx_current =
1266 (cyg_uint8 *)CYGARC_UNCACHED_ADDRESS(rltk8139_info->rx_ring +
1268 rltk8139_info->rx_size = length;
1270 /* Tell eCos about the packet */
1271 (sc->funs->eth_drv->recv)(sc, length);
1275 * Update CAPR. CAPR must be aligned to a 32 bit boundary, and should
1276 * point 16 bytes before it's actual position.
1278 rx_pos = ((rx_pos + length + 8 + 3) & ~3) % RX_BUF_LEN;
1279 OUTW((rx_pos - 16) % RX_BUF_LEN, rltk8139_info->base_address + CAPR);
1283 if (status & IR_RXOVW) {
1285 * In case of a receive buffer overflow, the RealTek data sheet claims we
1286 * should update CAPR and then write a '1'Â to ROK in ISR. However, none of
1287 * the other 8139 drivers I have looked at do this, so we will just reset
1290 #ifdef DEBUG_RLTK8139_DRIVER
1291 diag_printf("rltk8139_deliver(%s): receive buffer overflow\n",
1298 if (status & IR_FOVW) {
1300 * Rx FIFO overflow. According to RealTek's data sheet, this is cleared
1301 * by writing a '1' to RXOVW. Again, none of the 8139 drivers I have
1302 * seen actually do this, so we reset the chip instead.
1304 #ifdef DEBUG_RLTK8139_DRIVER
1305 diag_printf("rltk8139_deliver(%s): receive FIFO overflow\n",
1312 if (status & IR_FUN) {
1314 * Packet underrun or link change interrupt.
1315 * A cable was packet underrun or re-connected ?
1317 #ifdef DEBUG_RLTK8139_DRIVER
1318 diag_printf("rltk8139_deliver(%s): packet underrun or link change\n",
1323 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
1324 /* Finally, reenable interrupts */
1325 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_MASK_INTERRUPTS_IN_8139
1326 OUTW(RLTK8139_IRQ, rltk8139_info->base_address + IMR);
1328 cyg_interrupt_unmask(rltk8139_info->vector);
1335 * '_poll' does the same thing as '_deliver'. It is called periodically when
1336 * the ethernet driver is operated in non-interrupt mode, for instance by
1340 rltk8139_poll(struct eth_drv_sc *sc)
1342 Rltk8139_t *rltk8139_info;
1346 #ifdef DEBUG_RLTK8139_DRIVER
1347 diag_printf("rltk8139_poll(%s)\n", sc->dev_name);
1350 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
1353 * Get the current interrupt status. If anything changed, call
1356 if ((isr = INW(rltk8139_info->base_address + ISR)))
1357 rltk8139_deliver(sc);
1362 * Return the interrupt vector used by this device.
1365 rltk8139_int_vector(struct eth_drv_sc *sc)
1367 return ((Rltk8139_t *)(sc->driver_private))->vector;
1372 * Quick and dirty register dump. This is somewhat dangerous, since
1373 * we read the register space 32 bits at a time, regardless of actual
1376 #ifdef DEBUG_RLTK8139_DRIVER
1378 rltk8139_print_state(struct eth_drv_sc *sc) {
1380 Rltk8139_t *rltk8139_info;
1383 rltk8139_info = (Rltk8139_t *)(sc->driver_private);
1385 for (i = IDR0; i < FFER; i += 16) {
1386 diag_printf("8139 reg address 0x%02x = 0x%08x", i,
1387 INL(rltk8139_info->base_address + i));
1388 diag_printf(" 0x%08x", INL(rltk8139_info->base_address + i + 4));
1389 diag_printf(" 0x%08x", INL(rltk8139_info->base_address + i + 8));
1390 diag_printf(" 0x%08x\n", INL(rltk8139_info->base_address + i + 12));
1396 #ifdef CYGPKG_DEVS_ETH_RLTK_8139_WRITE_EEPROM
1398 * Read mac_address from EEPROM.
1401 rltk8139_eeprom_read( char *rtl_addr, cyg_uint8 eeprom_cmd, cyg_uint8 eeprom_addr )
1403 cyg_uint8 read_data; // read from eeprom bit data
1404 cyg_uint8 org_param; // original register parameter
1405 cyg_uint8 mask_bit8; // mask bit
1406 int icount; // for loop counter
1408 // get old parameter
1409 HAL_READ_UINT8( rtl_addr, org_param );
1412 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON );
1416 for(icount = 0; icount < 3; icount++){
1417 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_cmd ));
1423 for(icount = 0; icount < 6; icount++){
1424 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_addr ));
1430 for(icount = 0; icount < 16; icount++){
1431 EEPROM_RD_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS, read_data );
1435 EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
1436 EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
1438 // put old parameter
1439 HAL_WRITE_UINT8(rtl_addr, org_param);
1446 * Write in mac_address at EEPROM.
1449 rltk8139_eeprom_write( char *rtl_addr, cyg_uint8 eeprom_cmd, cyg_uint8 eeprom_addr, cyg_uint16 src_data )
1451 cyg_uint8 read_data; // read from eeprom bit data
1452 cyg_uint8 org_param; // original register parameter
1453 cyg_uint8 mask_bit8; // mask bit
1454 cyg_uint16 mask_bit16; // mask bit for write data
1455 int icount; // for loop counter
1457 // get old parameter
1458 HAL_READ_UINT8( rtl_addr, org_param );
1461 EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
1462 EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EESK );
1463 EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
1465 // set EWEN (eeprom write enable)
1466 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EEDI );
1467 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
1468 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
1469 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EEDI );
1470 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EEDI );
1471 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
1472 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
1473 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
1474 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
1475 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON );
1479 for(icount = 0; icount < 3; icount++){
1480 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_cmd ));
1486 for(icount = 0; icount < 6; icount++){
1487 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit8, eeprom_addr ));
1492 mask_bit16 = 0x8000;
1493 for(icount = 0; icount < 16; icount++){
1494 EEPROM_WR_DATAPULSE( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_MASK( mask_bit16, src_data ));
1499 EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
1500 EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EESK );
1501 EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON );
1503 // write ready check
1504 EEPROM_WR_DATA( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
1506 // wait busy disable
1509 cyg_thread_delay( 1 );
1510 HAL_WRITE_UINT8( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS | EEPROM_PG_EESK );
1511 HAL_WRITE_UINT8( rtl_addr, EEPROM_PG_ON | EEPROM_PG_EECS );
1512 HAL_READ_UINT8( rtl_addr, read_data );
1513 if(( read_data & EEPROM_PG_EEDO ) != 0 ){
1516 if( icount++ >= EEPROM_WR_BUSY_RETRIES ){
1517 diag_printf("EEPROM write wait error adr=0x%02x data=0x%04x\n", eeprom_addr, src_data );
1521 HAL_WRITE_UINT8( rtl_addr, EEPROM_PG_ON );
1523 // put old parameter
1524 HAL_WRITE_UINT8( rtl_addr, org_param );