1 #ifndef CYGONCE_DEVS_ETH_REALTEK_8139_INFO_H
2 #define CYGONCE_DEVS_ETH_REALTEK_8139_INFO_H
3 /*==========================================================================
8 //==========================================================================
9 //####ECOSGPLCOPYRIGHTBEGIN####
10 // -------------------------------------------
11 // This file is part of eCos, the Embedded Configurable Operating System.
12 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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29 // with other works to produce a work based on this file, this file does not
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39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //==========================================================================
42 //#####DESCRIPTIONBEGIN####
44 // Author(s): Eric Doenges
45 // Contributors: Chris Nimmers, Gary Thomas, Andy Dyer
49 //####DESCRIPTIONEND####
51 #include <pkgconf/devs_eth_rltk_8139.h>
55 * Used to define all vendor/device ID combinations we know about to find
64 #define PCI_ANY_ID (0xFFFF)
67 * Valid receive buffer sizes are 8k+16, 16k+16, 32k+16, or 64k+16.
68 * For the last case, WRAP mode should not be enabled. Since we do not
69 * currently want to support unwrapped mode, do not use 64k+16 at this
70 * point. The buffer length is set via the configuration mechanism.
72 #if (CYGNUM_DEVS_ETH_RLTK_8139_RX_BUF_LEN_IDX < 0) |\
73 (CYGNUM_DEVS_ETH_RLTK_8139_RX_BUF_LEN_IDX > 2)
74 #error "The receive ring size index must be in the range of 0 to 2"
76 #define RX_BUF_LEN (8192 << (CYGNUM_DEVS_ETH_RLTK_8139_RX_BUF_LEN_IDX))
78 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
79 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
81 /* Number of Tx descriptor registers. */
85 * Max supported ethernet frame size. The 8139 cannot transmit packets more
86 * than 1792 bytes long. Also, since transmit buffers must be 32-bit
87 * aligned, MAX_ETH_FRAME_SIZE should always be a multiple of 4.
89 #define MIN_ETH_FRAME_SIZE 60 /* without FCS */
90 #define MAX_ETH_FRAME_SIZE 1536 /* is this with/without FCS ? */
92 /* Size of the Tx buffers. */
93 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
94 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
96 /* Rx buffer level before first PCI transfer ('5' is 512 bytes) */
97 #define RX_FIFO_THRESH 5
100 * Maximum PCI rx and tx bursts. This value ranges from '0' (16 bytes)
101 * to '7' (unlimited), with MXDMA = 2^(4 + 'value').
103 #define RX_DMA_BURST 6
104 #define TX_DMA_BURST 6
107 * Device driver private data
110 /* Device number. Used for actually finding the device */
111 cyg_uint32 device_num;
113 /* Receive buffer ring area */
116 /* Transmit buffer area */
117 cyg_uint8 *tx_buffer;
120 cyg_pci_device_id pci_device_id;
122 /* Address for memory mapped I/O */
123 cyg_uint32 base_address;
125 /* Our current MAC address */
126 unsigned char mac[6];
128 /* tx FIFO threshold. */
129 cyg_uint8 tx_threshold;
131 /* This is the first free descriptor. */
134 /* This is the number of currently free descriptors */
135 int tx_num_free_desc;
137 /* Keys to match _send calls with the tx_done callback */
138 unsigned long tx_desc_key[NUM_TX_DESC];
141 * This is used to (temporarily) store the address of the current
142 * received packet. We save it here to avoid having to calculate it
145 cyg_uint8 *rx_current;
148 /* Interrupt handling stuff */
150 cyg_handle_t interrupt_handle;
151 cyg_interrupt interrupt;
153 /* device ISR priority */
154 cyg_priority_t isr_priority;
160 * Register offsets and bit definitions. These use the names in the 8139
161 * data sheet, not those found e.g. in the Linux driver for the 8139.
164 IDR0 = 0x0, /* mac address, seemingly in big-endian order */
170 MAR0 = 0x8, /* multicast registers (0-7) */
178 TSD0 = 0x10, /* L, transmit status of descriptor 0 */
182 TSAD0 = 0x20, /* L, transmit start address of descriptor 0 */
186 RBSTART = 0x30, /* L, receive buffer start address */
187 ERBCR = 0x34, /* W, early receive byte count register */
188 ERSR = 0x36, /* B, early receive status register */
189 CR = 0x37, /* B, command register */
190 CAPR = 0x38, /* W, current address of packet read */
191 CBR = 0x3A, /* W, current buffer address */
192 IMR = 0x3C, /* W, interrupt mask register */
193 ISR = 0x3E, /* W, interrupt status register */
194 TCR = 0x40, /* L, transmit configuration register */
195 RCR = 0x44, /* L, receive configuration register */
196 TCTR = 0x48, /* L, timer count register */
197 MPC = 0x4C, /* L, missed packet counter */
198 CR9346 = 0x50, /* B, 93C46 (serial eeprom) command register */
199 CONFIG0 = 0x51, /* B, configuration register 0 */
200 CONFIG1 = 0x52, /* B, configuration register 1 */
201 TIMERINT= 0x54, /* L, timer interrupt register */
202 MSR = 0x58, /* B, media status register */
203 CONFIG3 = 0x59, /* B, configuration register 0 */
204 CONFIG4 = 0x5A, /* B, configuration register 1 */
205 MULINT = 0x5C, /* W, multiple interrupt select */
206 RERID = 0x5E, /* B, PCI revision ID; should be 0x10 */
207 TSAD = 0x60, /* W, transmit status of all descriptors */
208 BMCR = 0x62, /* W, basic mode control register */
209 BMSR = 0x64, /* W, basic mode status register */
210 ANAR = 0x66, /* W, auto-negotiation advertisement register */
211 ANLPAR = 0x68, /* W, auto-negotiation link partner register */
212 ANER = 0x6A, /* W, auto-negotiation expansion register */
213 DIS = 0x6C, /* W, disconnect counter */
214 FCSC = 0x6E, /* W, false carrier sense counter */
215 NWAYTR = 0x70, /* W, N-way test register */
216 REC = 0x72, /* W, RX_ER counter */
217 CSCR = 0x74, /* W, CS configuration register */
218 PHY1_PARM = 0x78, /* L, PHY parameter 1 */
219 TW_PARM = 0x7C, /* L, twister parameter */
220 PHY2_PARM = 0x80, /* B, PHY parameter 2 */
221 CRC0 = 0x84, /* B, power management CRC register for wakeup frame 0 */
222 CRC1 = 0x85, /* B, power management CRC register for wakeup frame 1 */
223 CRC2 = 0x86, /* B, power management CRC register for wakeup frame 2 */
224 CRC3 = 0x87, /* B, power management CRC register for wakeup frame 3 */
225 CRC4 = 0x88, /* B, power management CRC register for wakeup frame 4 */
226 CRC5 = 0x89, /* B, power management CRC register for wakeup frame 5 */
227 CRC6 = 0x8A, /* B, power management CRC register for wakeup frame 6 */
228 CRC7 = 0x8B, /* B, power management CRC register for wakeup frame 7 */
229 WAKEUP0 = 0x8C, /* Q, power management wakeup frame 0 (64 bits) */
230 WAKEUP1 = 0x94, /* Q, power management wakeup frame 1 (64 bits) */
231 WAKEUP2 = 0x9C, /* Q, power management wakeup frame 2 (64 bits) */
232 WAKEUP3 = 0xA4, /* Q, power management wakeup frame 3 (64 bits) */
233 WAKEUP4 = 0xAC, /* Q, power management wakeup frame 4 (64 bits) */
234 WAKEUP5 = 0xB4, /* Q, power management wakeup frame 5 (64 bits) */
235 WAKEUP6 = 0xBC, /* Q, power management wakeup frame 6 (64 bits) */
236 WAKEUP7 = 0xC4, /* Q, power management wakeup frame 7 (64 bits) */
237 LSBCRC0 = 0xCC, /* B, LSB of mask byte of wakeup frame 0 offset 12 to 75 */
238 LSBCRC1 = 0xCD, /* B, LSB of mask byte of wakeup frame 1 offset 12 to 75 */
239 LSBCRC2 = 0xCE, /* B, LSB of mask byte of wakeup frame 2 offset 12 to 75 */
240 LSBCRC3 = 0xCF, /* B, LSB of mask byte of wakeup frame 3 offset 12 to 75 */
241 LSBCRC4 = 0xD0, /* B, LSB of mask byte of wakeup frame 4 offset 12 to 75 */
242 LSBCRC5 = 0xD1, /* B, LSB of mask byte of wakeup frame 5 offset 12 to 75 */
243 LSBCRC6 = 0xD2, /* B, LSB of mask byte of wakeup frame 6 offset 12 to 75 */
244 LSBCRC7 = 0xD3, /* B, LSB of mask byte of wakeup frame 7 offset 12 to 75 */
245 FLASH = 0xD4, /* L, flash memory read/write register */
246 CONFIG5 = 0xD8, /* B, configuration register #5 */
247 FER = 0xF0, /* L, function event register (CardBus only) */
248 FEMR = 0xF4, /* L, function event mask register (CardBus only) */
249 FPSR = 0xF8, /* L, function present state register (CardBus only) */
250 FFER = 0xFC /* L, function force event register (CardBus only) */
253 /* Receive status register in Rx packet header */
255 MAR = (1<<15), /* multicast address received */
256 PAM = (1<<14), /* physical address matched */
257 BAR = (1<<13), /* broadcast address received */
258 ISE = (1<<5), /* invalid symbol error */
259 RUNT = (1<<4), /* runt packet (<64 bytes) received */
260 LONG = (1<<3), /* long packet (>4K bytes) received */
261 CRC = (1<<2), /* CRC error */
262 FAE = (1<<1), /* frame alignment error */
263 ROK = (1<<0) /* receive OK */
266 /* Transmit status register */
268 CRS = (1<<31), /* carrier sense lost */
269 TABT = (1<<30), /* transmit abort */
270 OWC = (1<<29), /* out of window collision */
271 CDH = (1<<28), /* CD heart beat */
273 NCC = (0xF<<24), /* number of collision count */
275 ERTXTH = (0x1F<<16), /* early tx threshold, in multiples of 32 bytes */
276 TOK = (1<<15), /* transmission OK */
277 TUN = (1<<14), /* transmit FIFO underrun */
278 OWN = (1<<13), /* own */
279 SIZE = 0xFFF /* descriptor size */
282 /* Command register */
284 RST = (1<<4), /* reset */
285 RE = (1<<3), /* receiver enable */
286 TE = (1<<2), /* transmitter enable */
287 BUFE = (1<<0) /* buffer empty */
290 /* Transmit configuration register */
292 CLRABT = (1<<0) /* clear abort */
295 /* Receive configuration register */
297 ERTH_SHIFT = 24, /* Early Rx threshold bits (4) */
298 MULERINT = (1<<17), /* multiple early interrupt */
299 RER8 = (1<<16), /* ? */
300 RXFTH_SHIFT= 13, /* Rx FIFO threshold */
301 RBLEN_SHIFT= 11, /* Rx buffer length */
302 MXDMA_SHIFT= 8, /* max DMA burst size per Rx DMA burst */
303 WRAP = (1<<7), /* WRAP mode */
304 SEL9356 = (1<<6), /* EEPROM select */
305 AER = (1<<5), /* accept error packets */
306 AR = (1<<4), /* accept runt packets */
307 AB = (1<<3), /* accept broadcast packets */
308 AM = (1<<2), /* accept multicast packets */
309 APM = (1<<1), /* accept physical match packets (our MAC) */
310 AAP = (1<<0), /* accept physical address packets (any MAC) */
313 /* TSAD (transmit status of all descriptors */
333 /* Interrupt mask/status register */
335 IR_SERR = (1<<15), /* system error interrupt */
336 IR_TIMEOUT = (1<<14), /* time out interrupt */
337 IR_LENCHG = (1<<13), /* cable length change interrupt */
338 IR_FOVW = (1<<6), /* Rx FIFO overflow */
339 IR_FUN = (1<<5), /* Packet underrun or link change interrupt */
340 IR_RXOVW = (1<<4), /* Rx buffer overflow */
341 IR_TER = (1<<3), /* transmit error interrupt */
342 IR_TOK = (1<<2), /* transmit OK interrupt */
343 IR_RER = (1<<1), /* receive error interrupt */
344 IR_ROK = (1<<0) /* receive OK interrupt */
347 /* Packet header bits */
349 HDR_MAR = (1<<15), /* multicast address received */
350 HDR_PAM = (1<<14), /* physical address matched */
351 HDR_BAR = (1<<13), /* broadcast address matched */
352 HDR_ISE = (1<<5), /* invalid symbol error */
353 HDR_RUNT = (1<<4), /* runt packet received (packet < 64 bytes) */
354 HDR_LONG = (1<<3), /* long packet (>4k) */
355 HDR_CRC = (1<<2), /* CRC error */
356 HDR_FAE = (1<<1), /* frame alignment error */
357 HDR_ROK = (1<<0) /* receive OK */
362 * Define some options to use
364 #define TXCFG ((0x3 << 24) | (TX_DMA_BURST << MXDMA_SHIFT))
365 #define RXCFG ((RX_FIFO_THRESH << RXFTH_SHIFT) |\
366 (RX_BUF_LEN_IDX << RBLEN_SHIFT) |\
367 (RX_DMA_BURST << MXDMA_SHIFT) |\
370 #endif /* ifndef CYGONCE_DEVS_ETH_REALTEK_8139_INFO_H */