1 /*=============================================================================
5 // HAL diagnostic output code
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //===========================================================================*/
42 #include <pkgconf/hal.h>
44 #include <cyg/infra/cyg_type.h> // base types
45 #include <cyg/infra/cyg_trac.h> // tracing macros
46 #include <cyg/infra/cyg_ass.h> // assertion macros
48 #include <cyg/hal/hal_arch.h> // basic machine info
49 #include <cyg/hal/hal_intr.h> // interrupt macros
50 #include <cyg/hal/hal_io.h> // IO macros
51 #include <cyg/hal/hal_diag.h>
52 #include <cyg/hal/hal_if.h> // Calling-if API
53 #include <cyg/hal/drv_api.h> // driver API
54 #include <cyg/hal/hal_misc.h> // Helper functions
55 #include <cyg/hal/hal_soc.h> // Hardware definitions
56 #include <cyg/hal/fsl_board.h> // Platform specifics
58 static void cyg_hal_plf_duart_init(void);
59 extern void cyg_hal_plf_serial_init(void);
61 void cyg_hal_plf_comms_init(void)
63 static int initialized = 0;
69 cyg_hal_plf_duart_init();
70 cyg_hal_plf_serial_init();
73 //=============================================================================
74 // ST16552 DUART driver
75 //=============================================================================
77 //-----------------------------------------------------------------------------
78 // Only one external UART.
79 #define CYG_DEV_SERIAL_BASE_A (BOARD_CS_UART_BASE + 0x00)
81 //-----------------------------------------------------------------------------
82 // Based on 3.6864 MHz xtal
83 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
84 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
85 #define CYG_DEV_SERIAL_BAUD_LSB 0x18
87 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
88 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
89 #define CYG_DEV_SERIAL_BAUD_LSB 0x0C
91 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
92 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
93 #define CYG_DEV_SERIAL_BAUD_LSB 0x06
95 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
96 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
97 #define CYG_DEV_SERIAL_BAUD_LSB 0x04
99 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
100 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
101 #define CYG_DEV_SERIAL_BAUD_LSB 0x02
104 #ifndef CYG_DEV_SERIAL_BAUD_MSB
105 #error Missing/incorrect serial baud rate defined - CDL error?
108 //-----------------------------------------------------------------------------
109 // Define the serial registers. The board is equipped with a 16552
112 #if defined (EXT_UART_x16)
113 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
114 #define HAL_READ_UINT_UART HAL_READ_UINT16
115 typedef cyg_uint16 uart_width;
116 #elif defined (EXT_UART_x32)
117 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT32
118 #define HAL_READ_UINT_UART HAL_READ_UINT32
119 typedef cyg_uint32 uart_width;
121 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
122 #define HAL_READ_UINT_UART HAL_READ_UINT8
123 typedef cyg_uint8 uart_width;
126 #define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0
127 #define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
128 #define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
129 #define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0
130 #define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
131 #define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0
132 #define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0
133 #define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1
134 #define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write
135 #define CYG_DEV_SERIAL_MCR 0x04
136 #define CYG_DEV_SERIAL_MCR_A 0x04
137 #define CYG_DEV_SERIAL_MCR_B 0x04
138 #define CYG_DEV_SERIAL_LSR 0x05 // line status register, read
139 #define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read
140 #define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register
142 // The interrupt enable register bits.
143 #define SIO_IER_ERDAI 0x01 // enable received data available irq
144 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
145 #define SIO_IER_ELSI 0x04 // enable receiver line status irq
146 #define SIO_IER_EMSI 0x08 // enable modem status interrupt
148 // The interrupt identification register bits.
149 #define SIO_IIR_IP 0x01 // 0 if interrupt pending
150 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
154 // The line status register bits.
155 #define SIO_LSR_DR 0x01 // data ready
156 #define SIO_LSR_OE 0x02 // overrun error
157 #define SIO_LSR_PE 0x04 // parity error
158 #define SIO_LSR_FE 0x08 // framing error
159 #define SIO_LSR_BI 0x10 // break interrupt
160 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
161 #define SIO_LSR_TEMT 0x40 // transmitter register empty
162 #define SIO_LSR_ERR 0x80 // any error condition
164 // The modem status register bits.
165 #define SIO_MSR_DCTS 0x01 // delta clear to send
166 #define SIO_MSR_DDSR 0x02 // delta data set ready
167 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
168 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
169 #define SIO_MSR_CTS 0x10 // clear to send
170 #define SIO_MSR_DSR 0x20 // data set ready
171 #define SIO_MSR_RI 0x40 // ring indicator
172 #define SIO_MSR_DCD 0x80 // data carrier detect
174 // The line control register bits.
175 #define SIO_LCR_WLS0 0x01 // word length select bit 0
176 #define SIO_LCR_WLS1 0x02 // word length select bit 1
177 #define SIO_LCR_STB 0x04 // number of stop bits
178 #define SIO_LCR_PEN 0x08 // parity enable
179 #define SIO_LCR_EPS 0x10 // even parity select
180 #define SIO_LCR_SP 0x20 // stick parity
181 #define SIO_LCR_SB 0x40 // set break
182 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
184 // The FIFO control register
185 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
186 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
187 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
189 //-----------------------------------------------------------------------------
193 cyg_int32 msec_timeout;
197 static channel_data_t channels[] = {
198 #if CYGHWR_HAL_ARM_DUART_UARTA != 0
199 {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
201 #if CYGHWR_HAL_ARM_DUART_UARTB != 0
202 {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
206 //-----------------------------------------------------------------------------
208 static void init_duart_channel(channel_data_t* __ch_data)
210 uart_width* base = __ch_data->base;
214 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
215 SIO_LCR_WLS0 | SIO_LCR_WLS1);
217 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
219 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
220 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
221 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
222 lcr &= ~SIO_LCR_DLAB;
223 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
224 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
227 //#define x_debug_uart_log_buf
228 #ifdef x_debug_uart_log_buf
229 #define x_DIAG_BUFSIZE 2048
230 static char __x_log_buf[x_DIAG_BUFSIZE];
231 static int x_diag_bp = 0;
234 extern unsigned int g_board_type;
236 void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
238 uart_width* base = ((channel_data_t*)__ch_data)->base;
241 #ifdef x_debug_uart_log_buf
242 __x_log_buf[x_diag_bp++] = c;
244 CYGARC_HAL_SAVE_GP();
247 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
248 } while ((lsr & SIO_LSR_THRE) == 0);
250 HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
252 // Hang around until the character has been safely sent.
254 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
255 } while ((lsr & SIO_LSR_THRE) == 0);
257 CYGARC_HAL_RESTORE_GP();
260 static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
262 uart_width* base = ((channel_data_t*)__ch_data)->base;
263 uart_width lsr, ch16;
265 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
266 if ((lsr & SIO_LSR_DR) == 0)
269 HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
271 *ch = (cyg_uint8) (ch16 & 0x00FF);
276 cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
280 CYGARC_HAL_SAVE_GP();
282 while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
284 CYGARC_HAL_RESTORE_GP();
288 static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
291 CYGARC_HAL_SAVE_GP();
294 cyg_hal_plf_duart_putc(__ch_data, *__buf++);
296 CYGARC_HAL_RESTORE_GP();
299 static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
302 CYGARC_HAL_SAVE_GP();
305 *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
307 CYGARC_HAL_RESTORE_GP();
310 cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
313 channel_data_t* chan = (channel_data_t*)__ch_data;
316 CYGARC_HAL_SAVE_GP();
318 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
320 res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
321 if (res || 0 == delay_count--)
324 CYGACC_CALL_IF_DELAY_US(100);
327 CYGARC_HAL_RESTORE_GP();
331 static int cyg_hal_plf_duart_control(void *__ch_data,
332 __comm_control_cmd_t __func, ...)
334 static int irq_state = 0;
335 channel_data_t* chan = (channel_data_t*)__ch_data;
339 CYGARC_HAL_SAVE_GP();
342 case __COMMCTL_IRQ_ENABLE:
343 HAL_INTERRUPT_UNMASK(chan->isr_vector);
344 HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
345 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
346 ier |= SIO_IER_ERDAI;
347 HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
350 case __COMMCTL_IRQ_DISABLE:
353 HAL_INTERRUPT_MASK(chan->isr_vector);
354 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
355 ier &= ~SIO_IER_ERDAI;
356 HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
358 case __COMMCTL_DBG_ISR_VECTOR:
359 ret = chan->isr_vector;
361 case __COMMCTL_SET_TIMEOUT:
365 va_start(ap, __func);
367 ret = chan->msec_timeout;
368 chan->msec_timeout = va_arg(ap, cyg_uint32);
376 CYGARC_HAL_RESTORE_GP();
380 static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
381 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
383 channel_data_t* chan = (channel_data_t*)__ch_data;
386 CYGARC_HAL_SAVE_GP();
388 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
389 _iir &= SIO_IIR_ID_MASK;
392 if ( ISR_Rx == _iir ) {
395 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
396 if (lsr & SIO_LSR_DR) {
398 HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
400 c8 = (cyg_uint8) (c & 0x00FF);
402 if (cyg_hal_is_break( &c8 , 1 ))
406 // Acknowledge the interrupt
407 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
408 res = CYG_ISR_HANDLED;
411 CYGARC_HAL_RESTORE_GP();
415 static void cyg_hal_plf_duart_init(void)
417 hal_virtual_comm_table_t* comm;
418 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
422 #define NUMOF(x) (sizeof(x)/sizeof(x[0]))
423 for (i = 0; i < NUMOF(channels); i++) {
424 HAL_INTERRUPT_MASK(channels[i].isr_vector);
425 init_duart_channel(&channels[i]);
426 CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
427 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
428 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
429 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
430 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
431 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
432 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
433 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
434 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
435 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
438 // Restore original console
439 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
442 //=============================================================================
443 // Compatibility with older stubs
444 //=============================================================================
446 //=============================================================================
447 // Compatibility with older stubs
448 //=============================================================================
450 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
452 #include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
454 #if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
455 #define __BASE CMA101_DUARTA
456 #define _INT CYGNUM_HAL_INTERRUPT_SERIAL_A
457 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
458 #define __BASE CMA101_DUARTB
459 #define _INT CYGNUM_HAL_INTERRUPT_SERIAL_B
464 #ifdef CYGSEM_HAL_ROM_MONITOR
465 #define CYG_HAL_STARTUP_ROM
466 #define CYG_HAL_STARTUP_ROMRAM
467 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
470 #if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
471 #define HAL_DIAG_USES_HARDWARE
472 #elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
473 #define HAL_DIAG_USES_HARDWARE
474 #elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
475 #define HAL_DIAG_USES_HARDWARE
478 static channel_data_t channel = {
479 (uart_width*) _BASE, 0, 0
482 #ifdef HAL_DIAG_USES_HARDWARE
484 void hal_diag_init(void)
487 char *msg = "\n\rARM eCos\n\r";
492 init_duart_channel(&channel);
494 while (*msg) hal_diag_write_char(*msg++);
498 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
499 #define DIAG_BUFSIZE 32
501 #define DIAG_BUFSIZE 2048
503 static char diag_buffer[DIAG_BUFSIZE];
504 static int diag_bp = 0;
507 void hal_diag_write_char(char c)
513 cyg_hal_plf_duart_putc(&channel, c)
516 diag_buffer[diag_bp++] = c;
517 if (diag_bp == DIAG_BUFSIZE) {
524 void hal_diag_read_char(char *c)
526 *c = cyg_hal_plf_duart_getc(&channel);
529 #else // HAL_DIAG relies on GDB
531 // Initialize diag port - assume GDB channel is already set up
532 void hal_diag_init(void)
534 if (0) init_duart_channel(&channel); // avoid warning
537 // Actually send character down the wire
538 static void hal_diag_write_char_serial(char c)
540 cyg_hal_plf_duart_putc(&channel, c);
543 static bool hal_diag_read_serial(char *c)
545 long timeout = 1000000000; // A long time...
547 while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
548 if (0 == --timeout) return false;
553 void hal_diag_read_char(char *c)
555 while (!hal_diag_read_serial(c)) ;
558 void hal_diag_write_char(char c)
560 static char line[100];
563 // No need to send CRs
564 if (c == '\r') return;
568 if (c == '\n' || pos == sizeof(line)) {
569 CYG_INTERRUPT_STATE old;
571 // Disable interrupts. This prevents GDB trying to interrupt us
572 // while we are in the middle of sending a packet. The serial
573 // receive interrupt will be seen when we re-enable interrupts
576 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
577 CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
579 HAL_DISABLE_INTERRUPTS(old);
583 static char hex[] = "0123456789ABCDEF";
588 hal_diag_write_char_serial('$');
589 hal_diag_write_char_serial('O');
591 for (i = 0; i < pos; i++) {
593 char h = hex[(ch>>4)&0xF];
594 char l = hex[ch&0xF];
595 hal_diag_write_char_serial(h);
596 hal_diag_write_char_serial(l);
600 hal_diag_write_char_serial('#');
601 hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
602 hal_diag_write_char_serial(hex[csum&0xF]);
604 // Wait for the ACK character '+' from GDB here and handle
605 // receiving a ^C instead. This is the reason for this clause
607 if (!hal_diag_read_serial(&c1))
608 continue; // No response - try sending packet again
611 break; // a good acknowledge
613 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
614 cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
616 // Ctrl-C: breakpoint.
617 cyg_hal_gdb_interrupt (__builtin_return_address(0));
621 // otherwise, loop round again
626 // And re-enable interrupts
627 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
628 CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
630 HAL_RESTORE_INTERRUPTS(old);
639 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
641 /*---------------------------------------------------------------------------*/