1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 #define CYGHWR_HAL_ROM_VADDR 0x0
62 //#define NFC_2K_BI_SWAP
64 // This macro represents the initial startup code for the platform
65 // r11 is reserved to contain chip rev info in this file
66 .macro _platform_setup1
67 FSL_BOARD_SETUP_START:
68 // invalidate I/D cache/TLB and drain write buffer
70 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
71 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
72 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
81 ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
82 and r3, r3, #0xFFFFFF00 // mask off the LSB
83 ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
84 mov r4, r4, lsr #8 // shift it to get the byte at addr 5
85 and r4, r4, #0xFF // throw away upper 3 bytes
86 add r3, r4, r3 // construct the word
87 str r3, [r0, #0x7D0] // write back
93 mov r0, #SDRAM_NON_FLASH_BOOT
94 ldr r1, AVIC_VECTOR0_ADDR_W
95 str r0, [r1] // for checking boot source from nand, nor or sdram
97 // setup System Controls
98 ldr r0, SOC_SYSCTRL_BASE_W
100 str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
101 ldr r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
102 and r1, r1, #0xFFFFFFF0
104 str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
108 init_drive_strength_start:
116 // check if sdram has been setup
117 cmp pc, #SDRAM_BASE_ADDR
119 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
120 blo HWInitialise_skip_SDRAM_setup
124 // Now we must boot from Flash
125 mov r0, #NOR_FLASH_BOOT
126 ldr r1, AVIC_VECTOR0_ADDR_W
132 HWInitialise_skip_SDRAM_setup:
135 add r2, r0, #0x800 // 2K window
137 blo Normal_Boot_Continue
139 bhi Normal_Boot_Continue
142 /* Copy image from flash to SDRAM first */
143 ldr r1, MXC_REDBOOT_ROM_START
145 1: ldmia r0!, {r3-r10}
152 and r0, pc, r1 /* offset of pc */
153 ldr r1, MXC_REDBOOT_ROM_START
162 // Check if x16/2kb page
163 ldr r7, SOC_SYSCTRL_BASE_W
165 ands r7, r7, #(1 << 5)
167 mov r0, #NAND_FLASH_BOOT
168 ldr r1, AVIC_VECTOR0_ADDR_W
171 ldr r1, AVIC_VECTOR1_ADDR_W
174 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
175 mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
176 add r2, r0, #0x800 //2K Page:: r2: end of 1st RAM buf. Doesn't change
177 addeq r2, r0, #0x200 //512 Page:: r2: end of 1st RAM buf. Doesn't change
178 add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
179 ldr r11, MXC_REDBOOT_ROM_START
180 add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
181 add r11, r11, r1 //r11: starting SDRAM address for copying. Updated constantly
183 //unlock internal buffer
188 // NFC_CMD_INPUT(FLASH_Read_Mode1);
192 // Check if x16/2kb page
193 ldr r7, SOC_SYSCTRL_BASE_W
195 ands r7, r7, #(1 << 5)
197 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
199 do_addr_input //1st addr cycle
201 do_addr_input //2nd addr cycle
203 do_addr_input //3rd addr cycle
205 do_addr_input //4th addr cycle
206 b end_of_nfc_addr_ops
209 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
211 do_addr_input //1st addr cycle
213 do_addr_input //2nd addr cycle
215 do_addr_input //3rd addr cycle
217 do_addr_input //4th addr cycle
219 do_addr_input //4th addr cycle
221 // NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
226 // NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
227 // writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
228 // NAND_FLASH_CONFIG1_REG);
232 // Check if x16/2kb page
233 ldr r7, SOC_SYSCTRL_BASE_W
235 ands r7, r7, #(1 << 5)
236 beq nfc_addr_data_output_done_512
238 // For 2K page - 2nd 512
253 #ifdef NFC_2K_BI_SWAP
254 ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
255 and r3, r3, #0xFFFFFF00 // mask off the LSB
256 ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
257 mov r4, r4, lsr #8 // shift it to get the byte at addr 5
258 and r4, r4, #0xFF // throw away upper 3 bytes
259 add r3, r4, r3 // construct the word
260 str r3, [r0, #0x7D0] // write back
262 // check for bad block
263 mov r3, r1, lsl #(32-17) // get rid of block number
264 cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
265 b nfc_addr_data_output_done
267 nfc_addr_data_output_done_512:
268 // check for bad block
269 mov r3, r1, lsl #(32-5-9) // get rid of block number
270 cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
272 nfc_addr_data_output_done:
273 b Copy_Good_Blk // workaround for now. See ENGR00067497
275 add r4, r0, #0x800 //r3 -> spare area buf 0
280 // really sucks. Bad block!!!!
283 // even suckier since we already read the first page!
285 // Check if x16/2kb page
286 ldr r7, SOC_SYSCTRL_BASE_W
288 ands r7, r7, #(1 << 5)
290 subeq r11, r11, #512 //rewind 1 page for the sdram pointer
291 subeq r1, r1, #512 //rewind 1 page for the flash pointer
294 subne r11, r11, #0x800 //rewind 1 page for the sdram pointer
295 subne r1, r1, #0x800 //rewind 1 page for the flash pointer
298 // Check if x16/2kb page
299 ldr r7, SOC_SYSCTRL_BASE_W
301 ands r7, r7, #(1 << 5)
303 addeq r1, r1, #(32*512)
304 addne r1, r1, #(64*2048)
309 1: ldmia r0!, {r3-r10}
314 bge NAND_Copy_Main_done
315 // Check if x16/2kb page
316 ldr r7, SOC_SYSCTRL_BASE_W
318 ands r7, r7, #(1 << 5)
327 Normal_Boot_Continue:
329 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
330 /* Copy image from flash to SDRAM first */
333 ldr r1, MXC_REDBOOT_ROM_START
335 beq HWInitialise_skip_SDRAM_copy
337 add r2, r0, #REDBOOT_IMAGE_SIZE
339 1: ldmia r0!, {r3-r10}
345 and r0, pc, r1 /* offset of pc */
346 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
352 #endif /* CYG_HAL_STARTUP_ROMRAM */
354 HWInitialise_skip_SDRAM_copy:
360 ldr r1, =(SOC_CRM_BASE)
361 ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
362 /*Get chip ID://eq:i.MX27 TO1; neq:i.MX27 TO2*/
363 ldr r1, =SOC_SI_ID_REG
365 ands r1, r1, #0xF0000000
367 orreq r2, r2, #0xF000
368 orrne r2, r2, #0x01C0
370 ldr r1, =(SOC_CRM_BASE)
371 str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
373 /* end of NAND clock divider setup */
375 // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
376 ldr r1, =(SOC_SYSCTRL_GPCR)
381 // Set up a stack [for calling C code]
382 ldr r1, =__startup_stack
383 ldr r2, =RAM_BANK0_BASE
391 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
392 orr r1, r1, #7 // enable MMU bit
393 mcr MMU_CP, 0, r1, MMU_Control, c0
394 mov pc,r2 /* Change address spaces */
400 // Save shadow copy of BCR, also hardware configuration
404 str r9,[r1] // Saved far above...
406 .endm // _platform_setup1
410 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
411 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
413 bx lr // do_wait_op_done
416 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
417 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
419 // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
420 strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
421 // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
422 mov r3, #FDO_PAGE_SPARE_VAL
423 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
426 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
427 #define PLATFORM_SETUP1
431 ldr r0, SOC_CRM_BASE_W
432 // disable MPLL/SPLL first
433 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
435 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
437 /* Get the chip version and configure PLLs*/
438 ldr r1, SOC_SI_ID_REG_W
440 ands r1, r1, #0xF0000000
444 ldrh r1, [r1, #PBC_VERSION]
445 ands r1, r1, #CLK_INPUT_27MHZ_SET
448 ldrne r1, CRM_MPCTL0_VAL2_W
449 ldreq r1, CRM_MPCTL0_VAL2_27MHZ_W
450 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
452 ldrne r1, CRM_SPCTL0_VAL2_W
453 ldreq r1, CRM_SPCTL0_VAL2_27MHZ_W
454 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
457 1: ldr r1, PBC_BASE_W
458 ldrh r1, [r1, #PBC_VERSION]
459 ands r1, r1, #CLK_INPUT_27MHZ_SET
462 ldrne r1, CRM_MPCTL0_VAL_W
463 ldreq r1, CRM_MPCTL0_VAL_27MHZ_W
464 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
466 ldrne r1, CRM_SPCTL0_VAL_W
467 ldreq r1, CRM_SPCTL0_VAL_27MHZ_W
468 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
470 // enable/restart SPLL/MPLL
471 2: ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
472 #ifdef PLL_REF_CLK_32768HZ
473 // Make sure to use CKIL
474 bic r1, r1, #(3 << 16)
476 orr r1, r1, #(3 << 16) // select 26MHz
478 orr r1, r1, #0x000C0000
479 orr r1, r1, #0x00000003
480 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
482 // add some delay here
487 //Check The chip version TO1 or TO2
488 ldr r1, SOC_SI_ID_REG_W
490 ands r1, r1, #0xF0000000
492 ldreq r2, SOC_CRM_CSCR_W
493 ldrne r2, SOC_CRM_CSCR2_W
494 str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
496 //for i.MX27 TO2, Set divider of H264_CLK to zero, NFC to 3.
497 ldrne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
498 bicne r2, r2, #0x0000FC00
499 strne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
502 /* Configure PCDR1 */
503 ldr r1, SOC_CRM_PCDR1_W
504 str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
506 // Configure PCCR0 and PCCR1
507 ldr r1, SOC_CRM_PCCR0_W
508 str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
510 ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
512 str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
513 // make default CLKO to be FCLK
514 ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
515 and r1, r1, #0xFFFFFFE0
517 str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
521 ldr r1, SOC_CS0_CTL_BASE_W
522 ldr r2, CS0_0x0000CC03
523 str r2, [r1, #CSCRU_OFFSET]
524 ldr r2, CS0_0xA0330D01
525 str r2, [r1, #CSCRL_OFFSET]
526 ldr r2, CS0_0x00220800
527 str r2, [r1, #CSCRA_OFFSET]
530 /* CS0 sync mode setup */
533 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
535 /* Flash reset command */
536 ldr r0, CS0_BASE_ADDR_W
540 ldr r2, CS0_CMD_0xAAA
545 ldr r2, CS0_CMD_0x554
550 ldr r2, CS0_CMD_0xAAA
554 /* Write flash config register */
555 ldr r1, CS0_CFG_0x66CA
557 /* Flash reset command */
561 ldr r0, =SOC_CS0_CTL_BASE
562 ldr r1, CS0_0x23524E80
563 str r1, [r0, #CSCRU_OFFSET]
564 ldr r1, CS0_0x10000D03
565 str r1, [r0, #CSCRL_OFFSET]
566 ldr r1, CS0_0x00720900
567 str r1, [r0, #CSCRA_OFFSET]
568 .endm /* init_cs0_sync */
570 .macro init_cs4 /* ADS board expanded IOs */
571 ldr r1, SOC_CS4_CTL_BASE_W
572 ldr r2, CS4_CSCRU_0x0000DCF6
573 str r2, [r1, #CSCRU_OFFSET]
574 ldr r2, CS4_CSCRL_0x444A4541
575 str r2, [r1, #CSCRL_OFFSET]
576 ldr r2, CS4_CSCRA_0x44443302
577 str r2, [r1, #CSCRA_OFFSET]
581 // setup AIPI1 and AIPI2
582 mov r0, #SOC_AIPI1_BASE
583 ldr r1, AIPI1_0x20040304
584 str r1, [r0] /* PSR0 */
585 ldr r2, AIPI1_0xDFFBFCFB
586 str r2, [r0, #4] /* PSR1 */
587 // set r0 = AIPI2 base
590 str r1, [r0] /* PSR0 */
592 str r2, [r0, #4] /* PSR1 */
596 ldr r0, SOC_MAX_BASE_W
597 add r1, r0, #MAX_SLAVE_PORT1_OFFSET
598 add r2, r0, #MAX_SLAVE_PORT2_OFFSET
599 add r0, r0, #MAX_SLAVE_PORT0_OFFSET
602 ldr r6, SOC_MAX_0x00302145 /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
603 str r6, [r0, #MAX_SLAVE_MPR_OFFSET] /* same for all slave ports */
604 str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
605 str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
606 str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
607 str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
608 str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
611 .macro init_drive_strength
612 ldr r0, SOC_SYSCTRL_BASE_W
613 ldr r1, DS_0x55555555
614 str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
615 str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
616 str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
617 ldr r1, DS_0x00005005
618 str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
619 ldr r1, DS_0x15555555
620 str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
621 .endm // init_drive_strength
623 .macro setup_sdram_ddr
624 ldr r0, SOC_ESDCTL_BASE_W
625 mov r2, #SOC_CSD0_BASE
626 mov r1, #0x8 // initial reset
628 // Hold for more than 200ns
637 //Check The chip version TO1 or TO2
638 ldr r1, SOC_SI_ID_REG_W
640 ands r1, r1, #0xF0000000
641 // add Latency on CAS only for TO2
642 // TO 1.0's ID = 0x0 ==>> CAS = 3
644 ldr r1, SDRAM_0x00795729
646 // now handles TO 2.x
648 ands r1, r1, #0xE0000000
649 // TO 2.0's ID = 0x1 => CAS = 4 due to the MPEG4 issue
650 ldreq r1, SDRAM_0x00795429
651 // subesquent TO's are OK w/ CAS = 3
652 ldrne r1, SDRAM_0x00795729
655 ldr r1, SDRAM_0x92200000
658 ldr r1, SDRAM_0xA2200000
662 ldr r1, SDRAM_0xB2200000
665 add r3, r2, #0x1000000
667 ldr r1, SDRAM_0x82228485
669 .endm // setup_sdram_ddr
672 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
673 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
674 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
676 .endm // nfc_cmd_input
680 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
681 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
682 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
684 .endm // do_addr_input
686 #define PLATFORM_VECTORS _platform_vectors
687 .macro _platform_vectors
688 .globl _board_BCR, _board_CFG
689 _board_BCR: .long 0 // Board Control register shadow
690 _board_CFG: .long 0 // Board Configuration (read at RESET)
693 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
694 CONST_0xFFF: .word 0xFFF
695 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
696 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
697 SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
698 SOC_MAX_BASE_W: .word SOC_MAX_BASE
699 SOC_MAX_0x00302145: .word 0x00302145
700 SOC_CRM_BASE_W: .word SOC_CRM_BASE
701 CRM_MPCTL0_VAL_W: .word CRM_MPCTL0_VAL
702 CRM_SPCTL0_VAL_W: .word CRM_SPCTL0_VAL
703 CRM_MPCTL0_VAL_27MHZ_W: .word CRM_MPCTL0_VAL_27MHZ
704 CRM_SPCTL0_VAL_27MHZ_W: .word CRM_SPCTL0_VAL_27MHZ
705 SOC_CRM_CSCR_W: .word CRM_CSCR_VAL
706 CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
707 CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
708 CRM_MPCTL0_VAL2_27MHZ_W: .word CRM_MPCTL0_VAL2_27MHZ
709 CRM_SPCTL0_VAL2_27MHZ_W: .word CRM_SPCTL0_VAL2_27MHZ
710 SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
711 SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
712 SOC_CRM_PCCR0_W: .word 0x3108480F
713 SOC_CS4_CTL_BASE_W: .word SOC_CS4_CTL_BASE
714 CS4_CSCRU_0x0000DCF6: .word 0x0000DCF6
715 CS4_CSCRL_0x444A4541: .word 0x444A4541
716 CS4_CSCRA_0x44443302: .word 0x44443302
717 NFC_BASE_W: .word NFC_BASE
718 SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
719 SDRAM_0x00795429: .word 0x00795429
720 SDRAM_0x00795729: .word 0x00795729
721 SDRAM_0x92200000: .word 0x92200000
722 SDRAM_0xA2200000: .word 0xA2200000
723 SDRAM_0xB2200000: .word 0xB2200000
724 SDRAM_0x82228485: .word 0x82228485
725 CS0_0x0000CC03: .word 0x0000CC03
726 CS0_0xA0330D01: .word 0xA0330D01
727 CS0_0x00220800: .word 0x00220800
728 CS0_0x23524E80: .word 0x23524E80
729 CS0_0x10000D03: .word 0x10000D03
730 CS0_0x00720900: .word 0x00720900
731 CS0_CMD_0xAAA: .word 0x0AAA
732 CS0_CMD_0x554: .word 0x0554
733 CS0_CFG_0x66CA: .word 0x66CA
734 CS0_BASE_ADDR_W: .word CS0_BASE_ADDR
735 SOC_CS0_CTL_BASE_W: .word SOC_CS0_CTL_BASE
736 DS_0x55555555: .word 0x55555555
737 DS_0x00005005: .word 0x00005005
738 DS_0x15555555: .word 0x15555555
739 AIPI1_0x20040304: .word 0x20040304
740 AIPI1_0xDFFBFCFB: .word 0xDFFBFCFB
741 PBC_BASE_W: .word PBC_BASE
742 SOC_SI_ID_REG_W: .word SOC_SI_ID_REG
744 /*---------------------------------------------------------------------------*/
745 /* end of hal_platform_setup.h */
746 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */