1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
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33 // License. However the source code for this file must still be made available
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 //#define BOOT_FROM_MMC
54 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
55 #define PLATFORM_SETUP1 _platform_setup1
56 #if defined(BOOT_FROM_MMC)
57 #define PLATFORM_PREAMBLE flash_header
59 #define CYGHWR_HAL_ARM_HAS_MMU
61 #ifdef CYG_HAL_STARTUP_ROMRAM
62 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
68 #define SDRAM_FULL_PAGE_BIT 0x100
69 #define SDRAM_FULL_PAGE_MODE 0x37
70 #define SDRAM_BURST_MODE 0x33
72 #define MMC_BLK_LEN 0x200
73 #define MMC_START_ADDR 0x0
74 #define MMC_LOAD_SIZE 0x30000
75 #define CYGHWR_HAL_ROM_VADDR 0x0
78 #define UNALIGNED_ACCESS_ENABLE
79 #define SET_T_BIT_DISABLE
80 #define BRANCH_PREDICTION_ENABLE
83 //#define TURN_OFF_IMPRECISE_ABORT
91 MMC_SDHC1_BASE_ADDR_W: .word MMC_SDHC1_BASE_ADDR
92 ESDHC_INTERRUPT_ENABLE_W: .word ESDHC_INTERRUPT_ENABLE
93 ESDHC_CLEAR_INTERRUPT_W: .word ESDHC_CLEAR_INTERRUPT
94 MXC_REDBOOT_ROM_ST_ADDR: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
95 REDBOOT_RESET_VECTOR: .word reset_vector
97 /* Check if booting from IRAM for MMC boot */
98 mov r0, #SDRAM_BASE_ADDR
101 setup_sdram ddr X32 DDR 0
105 ldr r0, REDBOOT_RESET_VECTOR
110 //Configure interface block and number of blocks 1 block and size is 512 Bytes
112 ldr r3, MMC_SDHC1_BASE_ADDR_W
113 str r2, [r3, #ESDHC_REG_BLK_LEN]
115 str r2, [r3, #ESDHC_REG_NOB]
116 //set block size and number of blocks of card
117 mov r1, #MMC_START_ADDR
120 ldr r11, MXC_REDBOOT_ROM_ST_ADDR
121 mov r12, #MMC_LOAD_SIZE
124 //set read data length, Comfigure command CMD16 for single block read
131 //set read data address
132 //CMD17 data_present Y
143 ldr r4, ESDHC_INTERRUPT_ENABLE_W
144 str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
146 ldr r4, [r3, #ESDHC_REG_INT_STATUS]
147 mov r2, #0x80 //ESDHC_STATUS_BUF_READ_RDY_MSK
151 four_times: //transfer data from SDHC buffer to ddr(4 words once)
152 ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
155 ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
158 ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
161 ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
167 check_tran_done: //check if the transfer is over
168 ldr r4, [r3, #ESDHC_REG_INT_STATUS]
169 mov r2, #0x800 //ESDHC_STATUS_TRANSFER_COMPLETE_MSK
179 .macro send_cmd_wait_resp
181 ldr r3, MMC_SDHC1_BASE_ADDR_W
183 str r4, [r3, #ESDHC_REG_CLK]
185 //wait until the clk has started
187 ldr r4, [r3, #ESDHC_REG_INT_STATUS]
192 //Clear Interrupt status register
193 ldr r4, ESDHC_CLEAR_INTERRUPT_W
194 str r4, [r3, #ESDHC_REG_INT_STATUS]
195 /* Enable Interrupt */
196 ldr r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
197 ldr r5, ESDHC_INTERRUPT_ENABLE_W
199 str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
201 /* Write Command Argument in Command Argument Register */
202 str r1, [r3, #ESDHC_REG_COMMAND]
203 str r0, [r3, #ESDHC_REG_COMMAND_TRANS_TYPE]
204 str r2, [r3, #ESDHC_REG_COMMAND_DAT_CONT]
206 2: //wait for responds
214 ldr r0, [r3, #ESDHC_REG_INT_STATUS]
221 str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
224 // This macro represents the initial startup code for the platform
225 // r11 is reserved to contain chip rev info in this file
226 .macro _platform_setup1
227 FSL_BOARD_SETUP_START:
230 * - invalidate I/D cache/TLB and drain write buffer;
231 * - invalidate L2 cache
233 * - branch predictions
235 #ifdef TURN_OFF_IMPRECISE_ABORT
241 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
242 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
243 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
245 /* Also setup the Peripheral Port Remap register inside the core */
246 ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
247 mcr p15, 0, r0, c15, c2, 4
249 /* Reload data from spare area to 0x400 of main area if booting from NAND */
258 /*** L2 Cache setup/invalidation/disable ***/
259 /* Disable L2 cache first */
260 mov r0, #L2CC_BASE_ADDR
261 ldr r2, [r0, #L2_CACHE_CTL_REG]
263 str r2, [r0, #L2_CACHE_CTL_REG]
265 * Configure L2 Cache:
266 * - 128k size(16k way)
267 * - 8-way associativity
268 * - 0 ws TAG/VALID/DIRTY
271 ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
272 and r1, r1, #0xFE000000
273 ldr r2, L2CACHE_PARAM
275 str r1, [r0, #L2_CACHE_AUX_CTL_REG]
279 str r1, [r0, #L2_CACHE_INV_WAY_REG]
281 /* Poll Invalidate By Way register */
282 ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
285 /*** End of L2 operations ***/
287 mov r0, #SDRAM_NON_FLASH_BOOT
288 ldr r1, AVIC_VECTOR0_ADDR_W
289 str r0, [r1] // for checking boot source from nand, nor or sdram
291 * End of ARM1136 init
302 ldr r11, =CHIP_REV_1_0
303 ldr r0, IIM_SREV_REG_VAL
306 ldrne r11, =CHIP_REV_1_1
308 init_cs0_async_start:
312 /* If SDRAM has been setup, bypass clock/WEIM setup */
314 ldreq r1, AVIC_VECTOR0_ADDR_W
318 cmp pc, #SDRAM_BASE_ADDR
320 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
321 blo HWInitialise_skip_SDRAM_setup
323 mov r0, #NOR_FLASH_BOOT
324 ldr r1, AVIC_VECTOR0_ADDR_W
334 beq HWInitialise_skip_SDRAM_setup
336 /* Based on chip rev, setup params for SDRAM controller */
338 mov r4, #SDRAM_BURST_MODE
341 #ifndef BOOT_FROM_MMC
342 /* Assuming DDR memory first */
343 setup_sdram ddr X32 DDR 0
346 HWInitialise_skip_SDRAM_setup:
349 add r2, r0, #0x800 // 2K window
351 blo Normal_Boot_Continue
353 bhi Normal_Boot_Continue
355 /* Copy image from flash to SDRAM first */
356 ldr r1, MXC_REDBOOT_ROM_START
358 1: ldmia r0!, {r3-r10}
364 and r0, pc, r1 /* offset of pc */
365 ldr r1, MXC_REDBOOT_ROM_START
373 // Check if x16/2kb page
374 ldr r7, CCM_BASE_ADDR_W
376 ands r7, r7, #(1 << 30)
378 mov r0, #NAND_FLASH_BOOT
379 ldr r1, AVIC_VECTOR0_ADDR_W
382 ldr r1, AVIC_VECTOR1_ADDR_W
385 mov r0, #NFC_BASE; //r0: nfc base. Reloaded after each page copying
386 mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
387 add r2, r0, #0x800 //r2: end of 3rd RAM buf. Doesn't change
388 addeq r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
389 add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
390 ldr r11, MXC_REDBOOT_ROM_START
391 add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
392 add r11, r11, r1 //r11: starting SDRAM address for copying. Updated constantly
394 //unlock internal buffer
399 // NFC_CMD_INPUT(FLASH_Read_Mode1);
403 // Check if x16/2kb page
404 ldr r7, CCM_BASE_ADDR_W
406 ands r7, r7, #(1 << 30)
408 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
410 do_addr_input //1st addr cycle
412 do_addr_input //2nd addr cycle
414 do_addr_input //3rd addr cycle
416 do_addr_input //4th addr cycle
417 b end_of_nfc_addr_ops
420 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
422 do_addr_input //1st addr cycle
424 do_addr_input //2nd addr cycle
426 do_addr_input //3rd addr cycle
428 do_addr_input //4th addr cycle
430 // NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
435 // NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
436 // writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
437 // NAND_FLASH_CONFIG1_REG);
441 // Check if x16/2kb page
442 ldr r7, CCM_BASE_ADDR_W
444 ands r7, r7, #(1 << 30)
445 beq nfc_addr_data_output_done_512
447 // For 2K page - 2nd 512
462 // check for bad block
463 mov r3, r1, lsl #(32-17) // get rid of block number
464 cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
465 b nfc_addr_data_output_done
467 nfc_addr_data_output_done_512:
468 // check for bad block
469 mov r3, r1, lsl #(32-5-9) // get rid of block number
470 cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
472 nfc_addr_data_output_done:
474 add r4, r0, #0x800 //r3 -> spare area buf 0
479 // really sucks. Bad block!!!!
482 // even suckier since we already read the first page!
483 // Check if x16/2kb page
484 ldr r7, CCM_BASE_ADDR_W
486 ands r7, r7, #(1 << 30)
488 subeq r11, r11, #512 //rewind 1 page for the sdram pointer
489 subeq r1, r1, #512 //rewind 1 page for the flash pointer
492 subne r11, r11, #0x800 //rewind 1 page for the sdram pointer
493 subne r1, r1, #0x800 //rewind 1 page for the flash pointer
496 // Check if x16/2kb page
497 ldr r7, CCM_BASE_ADDR_W
499 ands r7, r7, #(1 << 30)
501 addeq r1, r1, #(32*512)
502 addne r1, r1, #(64*2048)
507 1: ldmia r0!, {r3-r10}
512 bge NAND_Copy_Main_done
513 // Check if x16/2kb page
514 ldr r7, CCM_BASE_ADDR_W
516 ands r7, r7, #(1 << 30)
524 Normal_Boot_Continue:
526 #if defined(CYG_HAL_STARTUP_ROMRAM) || defined(BOOT_FROM_MMC) /* enable running from RAM */
527 /* Copy image from flash to SDRAM first */
530 ldr r1, MXC_REDBOOT_ROM_START
532 beq HWInitialise_skip_SDRAM_copy
534 add r2, r0, #REDBOOT_IMAGE_SIZE
536 1: ldmia r0!, {r3-r10}
542 and r0, pc, r1 /* offset of pc */
543 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
549 #endif /* CYG_HAL_STARTUP_ROMRAM */
551 HWInitialise_skip_SDRAM_copy:
558 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
562 // Set up a stack [for calling C code]
563 ldr r1, =__startup_stack
564 ldr r2, =RAM_BANK0_BASE
572 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
573 orr r1, r1, #7 // enable MMU bit
574 orr r1, r1, #0x800 // enable z bit
575 mcr MMU_CP, 0, r1, MMU_Control, c0
576 mov pc,r2 /* Change address spaces */
582 // Save shadow copy of BCR, also hardware configuration
586 str r9, [r1] // Saved far above...
588 .endm // _platform_setup1
592 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
593 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
595 bx lr // do_wait_op_done
598 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
599 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
601 // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
602 strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
603 // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
604 mov r3, #FDO_PAGE_SPARE_VAL
605 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
608 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
609 #define PLATFORM_SETUP1
614 .endm /* init_spba */
616 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
619 * Set all MPROTx to be non-bufferable, trusted for R/W,
620 * not forced to user-mode.
622 ldr r0, AIPS1_CTRL_BASE_ADDR_W
623 ldr r1, AIPS1_PARAM_W
626 ldr r0, AIPS2_CTRL_BASE_ADDR_W
631 * Clear the on and off peripheral modules Supervisor Protect bit
632 * for SDMA to access them. Did not change the AIPS control registers
633 * (offset 0x20) access type
635 ldr r0, AIPS1_CTRL_BASE_ADDR_W
642 and r1, r1, #0x00FFFFFF
645 ldr r0, AIPS2_CTRL_BASE_ADDR_W
652 and r1, r1, #0x00FFFFFF
654 .endm /* init_aips */
656 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
658 ldr r0, MAX_BASE_ADDR_W
659 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
661 str r1, [r0, #0x000] /* for S0 */
662 str r1, [r0, #0x100] /* for S1 */
663 str r1, [r0, #0x200] /* for S2 */
664 str r1, [r0, #0x300] /* for S3 */
665 str r1, [r0, #0x400] /* for S4 */
666 /* SGPCR - always park on last master */
668 str r1, [r0, #0x010] /* for S0 */
669 str r1, [r0, #0x110] /* for S1 */
670 str r1, [r0, #0x210] /* for S2 */
671 str r1, [r0, #0x310] /* for S3 */
672 str r1, [r0, #0x410] /* for S4 */
673 /* MGPCR - restore default values */
675 str r1, [r0, #0x800] /* for M0 */
676 str r1, [r0, #0x900] /* for M1 */
677 str r1, [r0, #0xA00] /* for M2 */
678 str r1, [r0, #0xB00] /* for M3 */
679 str r1, [r0, #0xC00] /* for M4 */
680 str r1, [r0, #0xD00] /* for M5 */
685 ldr r0, IPU_CTRL_BASE_ADDR_W
689 ldr r0, CCM_BASE_ADDR_W
690 ldr r2, CCM_CCMR_0x074B0BF5
691 ldr r3, CCM_CCMR_0x074B0BFD
692 ldr r4, CCM_CCMR_0x074B0B7D
694 // Make sure to use CKIH
695 ldr r1, [r0, #CLKCTL_CCMR]
696 bic r1, r1, #0x8 // disable PLL first
697 str r1, [r0, #CLKCTL_CCMR]
698 str r2, [r0, #CLKCTL_CCMR] // select CKIH (26MHz) as PLL ref clock
703 str r3, [r0, #CLKCTL_CCMR] // enable PLL
704 str r4, [r0, #CLKCTL_CCMR] // switch to PLL (SPLL for FIR)
707 ldrh r1, [r1, #PBC_BSTAT2]
708 ands r1, r1, #CLK_INPUT_27MHZ_SET
712 str r1, [r0, #CLKCTL_PDR0]
713 ldr r1, MPCTL_PARAM_W
714 ldrne r1, MPCTL_PARAM_532_27_W
715 str r1, [r0, #CLKCTL_MPCTL]
717 /* Set UPLL=240MHz, USB=60MHz */
718 ldr r1, CCM_PDR1_0x49FCFE7F
719 str r1, [r0, #CLKCTL_PDR1]
720 ldr r1, CCM_UPCTL_PARAM_240
721 ldrne r1, CCM_UPCTL_PARAM_240_27
722 str r1, [r0, #CLKCTL_UPCTL]
723 // default CLKO to 1/8 of the ARM core
725 add r1, r1, #0x00000006
726 str r1, [r0, #CLKCTL_COSR]
727 .endm /* init_clock */
731 /* Configure M3IF registers */
734 * M3IF Control Register (M3IFCTL)
735 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
736 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
737 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
738 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
739 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
740 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
741 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
742 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
747 str r0, [r1] /* M3IF control reg */
748 .endm /* init_m3if */
750 /* CS0 sync mode setup */
753 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
755 /* Flash reset command */
756 ldr r0, =CS0_BASE_ADDR
774 /* Write flash config register */
777 /* Flash reset command */
781 ldr r0, WEIM_CTRL_CS0_W
788 .endm /* init_cs0_sync */
790 /* CS0 async mode setup */
791 .macro init_cs0_async
792 /* Async flash mode */
793 ldr r0, WEIM_CTRL_CS0_W
794 ldr r1, CS0_CSCRU_0x11414C80
796 ldr r1, CS0_CSCRL_0x30000D03
798 ldr r1, CS0_CSCRA_0x00310800
800 .endm /* init_cs0_async */
802 /* CPLD on CS4 setup */
804 ldr r0, WEIM_CTRL_CS4_W
805 ldr r1, CS4_0x0000D843
807 ldr r1, CS4_0x22252521
809 ldr r1, CS4_0x22220A00
813 .macro setup_sdram, name, bus_width, mode, full_page
814 /* It sets the "Z" flag in the CPSR at the end of the macro */
816 ESDCTL_BASE_W: .word ESDCTL_BASE
817 SDRAM_0x0075E73A: .word 0x0075E73A
818 SDRAM_PARAM1_DDR: .word 0x4
819 SDRAM_PARAM1_SDR: .word 0x0
820 SDRAM_PARAM2_DDR: .word 0x80000F00
821 SDRAM_PARAM2_SDR: .word 0x80000400
822 SDRAM_PARAM3_DDR: .word 0x00100000
823 SDRAM_PARAM3_SDR: .word 0x0
824 SDRAM_PARAM4_X32: .word 0x00010000
825 SDRAM_PARAM4_X16: .word 0x0
826 SDRAM_0x55555555: .word 0x55555555
827 SDRAM_0xAAAAAAAA: .word 0xAAAAAAAA
828 SDRAM_0x92100000: .word 0x92100000
829 SDRAM_0xA2100000: .word 0xA2100000
830 SDRAM_0xB2100000: .word 0xB2100000
831 SDRAM_0x82116080: .word 0x82116080
833 ldr r0, ESDCTL_BASE_W
834 mov r2, #SDRAM_BASE_ADDR
835 ldr r1, SDRAM_0x0075E73A
837 ldr r1, =0x2 // reset
839 ldr r1, SDRAM_PARAM1_\mode
841 // Hold for more than 200ns
847 ldr r1, SDRAM_0x92100000
850 ldr r12, SDRAM_PARAM2_\mode
852 ldr r1, SDRAM_0xA2100000
856 ldr r1, SDRAM_0xB2100000
861 strb r1, [r2, #SDRAM_FULL_PAGE_MODE]
863 strb r1, [r2, #SDRAM_BURST_MODE]
869 ldr r3, SDRAM_0x82116080
870 ldr r4, SDRAM_PARAM3_\mode
872 ldr r4, SDRAM_PARAM4_\bus_width
875 add r3, r3, #0x100 /* Force to full page mode */
881 /* Below only for DDR */
884 ldrne r1, =0x0000000C
885 strne r1, [r0, #0x10]
886 /* Testing if it is truly DDR */
887 ldr r1, SDRAM_0x55555555
888 ldr r0, =SDRAM_BASE_ADDR
890 ldr r2, SDRAM_0xAAAAAAAA
897 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
898 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
899 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
901 .endm // nfc_cmd_input
905 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
906 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
907 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
909 .endm // do_addr_input
911 /* To support 133MHz DDR */
912 .macro init_drive_strength
914 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
915 * in SW_PAD_CTL registers
919 ldr r1, IOMUXC_BASE_ADDR_W
921 // Now r1 = (IOMUX_BASE_ADDR + 0x200)
923 bic r0, r0, #(1 << 12)
928 bic r0, r0, #(1 << 22)
933 bic r0, r0, #(1 << 2)
938 bic r0, r0, #(1 << 22)
943 bic r0, r0, #(1 << 22)
946 // DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
947 ldr r2, =22 // (0x2E0 - 0x288) / 4 = 22
950 bic r0, r0, #(1 << 22)
951 bic r0, r0, #(1 << 12)
952 bic r0, r0, #(1 << 2)
957 .endm /* init_drive_strength */
959 #define PLATFORM_VECTORS _platform_vectors
960 .macro _platform_vectors
961 .globl _board_BCR, _board_CFG
962 _board_BCR: .long 0 // Board Control register shadow
963 _board_CFG: .long 0 // Board Configuration (read at RESET)
966 ARM_PPMRR: .word 0x40000015
967 L2CACHE_PARAM: .word 0x00030024
968 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
969 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
970 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
971 AIPS1_PARAM_W: .word 0x77777777
972 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
973 MAX_PARAM1: .word 0x00302154
974 CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
975 M3IF_BASE_W: .word M3IF_BASE
976 WEIM_CTRL_CS0_W: .word WEIM_CTRL_CS0
977 CS0_CSCRU_0x11414C80: .word 0x11414C80
978 CS0_CSCRL_0x30000D03: .word 0x30000D03
979 CS0_CSCRA_0x00310800: .word 0x00310800
980 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
982 CCM_PDR0_W: .word PDR0_399_133_66
983 MPCTL_PARAM_W: .word MPCTL_PARAM_399
986 CCM_PDR0_W: .word PDR0_532_133_66
987 MPCTL_PARAM_W: .word MPCTL_PARAM_532
990 MPCTL_PARAM_532_27_W: .word MPCTL_PARAM_532_27
991 CCM_PDR1_0x49FCFE7F: .word 0x49FCFE7F
992 CCM_UPCTL_PARAM_240: .word UPCTL_PARAM_240
993 CCM_UPCTL_PARAM_240_27: .word UPCTL_PARAM_240_27
994 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
995 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
996 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
997 CONST_0x0FFF: .word 0x0FFF
998 CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
999 IPU_CTRL_BASE_ADDR_W: .word IPU_CTRL_BASE_ADDR
1000 CCM_CCMR_0x074B0BF5: .word 0x074B0BF5
1001 CCM_CCMR_0x074B0BFD: .word 0x074B0BFD
1002 CCM_CCMR_0x074B0B7D: .word 0x074B0B7D
1003 WEIM_CTRL_CS4_W: .word WEIM_CTRL_CS4
1004 CS4_0x0000D843: .word 0x0000D843
1005 CS4_0x22252521: .word 0x22252521
1006 CS4_0x22220A00: .word 0x22220A00
1008 /*---------------------------------------------------------------------------*/
1009 /* end of hal_platform_setup.h */
1010 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */