1 //==========================================================================
5 // HAL misc board support code for the TX37 board
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
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34 // this file might be covered by the GNU General Public License.
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
43 #include <pkgconf/hal.h>
44 #include <pkgconf/system.h>
46 #include CYGBLD_HAL_PLATFORM_H
48 #include <cyg/infra/cyg_type.h> // base types
49 #include <cyg/infra/cyg_trac.h> // tracing macros
50 #include <cyg/infra/cyg_ass.h> // assertion macros
52 #include <cyg/hal/hal_io.h> // IO macros
53 #include <cyg/hal/hal_arch.h> // Register state info
54 #include <cyg/hal/hal_diag.h>
55 #include <cyg/hal/hal_intr.h> // Interrupt names
56 #include <cyg/hal/hal_cache.h>
57 #include <cyg/hal/hal_soc.h> // Hardware definitions
58 #include <cyg/hal/karo_tx37.h> // Platform specifics
59 #include <cyg/infra/diag.h> // diag_printf
61 // All the MM table layout is here:
62 #include <cyg/hal/hal_mm.h>
64 void hal_mmu_init(void)
66 unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
70 * Set the TTB register
72 asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
75 * Set the Domain Access Control Register
77 i = ARM_ACCESS_DACR_DEFAULT;
78 asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
81 * First clear all TT entries - ie Set them to Faulting
83 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
85 /* Physical Virtual Size Attributes Function */
86 /* Base Base MB cached? buffered? access permissions */
87 /* xxx00000 xxx00000 */
88 X_ARM_MMU_SECTION(0x000, 0x200, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
89 X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
90 X_ARM_MMU_SECTION(0x400, 0x000, TX37_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
91 X_ARM_MMU_SECTION(0x400, 0x400, TX37_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
92 X_ARM_MMU_SECTION(0x400, 0x480, TX37_SDRAM_SIZE >> 20, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
93 X_ARM_MMU_SECTION(0x7ff, 0x7ff, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */
94 X_ARM_MMU_SECTION(0x800, 0x800, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
95 X_ARM_MMU_SECTION(0xB00, 0xB00, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */
99 // Platform specific initialization
102 static inline void set_reg(unsigned long addr, CYG_WORD32 set, CYG_WORD32 clr)
105 HAL_READ_UINT32(addr, val);
106 val = (val & ~clr) | set;
107 HAL_WRITE_UINT32(addr, val);
110 #define GPIO_BASE(grp) (GPIO1_BASE_ADDR + (((grp) - 1) << 14))
111 static inline void setup_gpio(int grp, int bit)
113 set_reg(GPIO_BASE(grp) + GPIO_DR, 0, 1 << bit);
114 set_reg(GPIO_BASE(grp) + GPIO_GDIR, 1 << bit, 0);
117 /* GPIOs to set up for TX27/Starterkit-5:
118 Function FCT GPIO Pad IOMUXC SW_PAD SW_PAD mode
120 FEC_MDC 4 GPIO3_1 CSPI1_MISO 0x138 0x398
121 FEC_MDIO 4 GPIO2_23 AUD5_WB_FS 0x130 0x390 0x5a8 0
122 FEC_RX_CLK 1 GPIO2_1 EIM_CS1 0x058 0x2b8 0x5b0 0
123 FEC_RX_DV 3 GPIO1_10 EIM_BCLK 0x064 0x2c4 0x5b4 0
124 FEC_RXD0 4 GPIO2_30 UART1_RI 0x174 0x3d4 0x5ac 1
125 FEC_RXD1 4 GPIO3_3 CSPI1_SS1 0x140 0x3a0
126 FEC_RXD2 4 GPIO3_5 CSPI2_MOSI 0x148 0x3a8
127 FEC_RXD3 4 GPIO3_6 CSPI2_MISO 0x14c 0x3ac
128 FEC_RX_ER 4 GPIO3_0 CSPI1_MOSI 0x134 0x394 0x5b8 1
129 FEC_TX_CLK 3 GPIO1_9 EIM_RW 0x068 0x2c8 0x5bc 0
130 FEC_TX_EN 3 GPIO1_13 EIM_OE 0x050 0x2b0
131 FEC_TXD0 4 GPIO2_31 UART1_DCD 0x178 0x3d8
132 FEC_TXD1 4 GPIO3_7 CSPI2_SS0 0x150 0x3b0
133 FEC_TXD2 4 GPIO3_8 CSPI2_SS1 0x154 0x3b4 :( reference Manual says: 0xBASE_
134 FEC_TXD3 4 GPIO3_9 CSPI2_SCLK 0x158 0x3b8
135 FEC_COL 1 GPIO2_0 EIM_CS0 0x054 0x2b4 0x5a0 0
136 FEC_CRS 4 GPIO3_2 CSPI1_SS0 0x13c 0x39c 0x5a4 1
137 FEC_TX_ER 4 GPIO3_4 CSPI1_SCLK 0x144 0x3a4
139 FEC_RESET# 1 GPIO1_7 GPIO1_7 0x22c 0x484
140 FEC_ENABLE 4 GPIO2_9 NANDF_CS1 0x088 0x2e8
142 OSC26M_ENABLE LP3972 GPIO2
144 static void fec_gpio_init(void)
146 /* setup GPIO data register to 0 and DDIR output for FEC PHY pins */
169 /* setup input mux for FEC pins */
170 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5a8, 0);
171 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5b0, 0);
172 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5b4, 0);
173 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5ac, 1);
174 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5b8, 1);
175 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5bc, 0);
176 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5a0, 0);
177 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x5a4, 1);
179 /* setup FEC PHY pins for GPIO function (with SION set) */
180 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x138, 4 | 0x10);
181 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x130, 4 | 0x10);
182 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x058, 1 | 0x10);
183 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x064, 3 | 0x10);
184 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x174, 4 | 0x10);
185 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x140, 4 | 0x10);
186 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x148, 4 | 0x10);
187 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x14c, 4 | 0x10);
188 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x134, 4 | 0x10);
189 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x068, 3 | 0x10);
190 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x050, 3 | 0x10);
191 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x178, 4 | 0x10);
192 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x150, 4 | 0x10);
193 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x154, 4 | 0x10);
194 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x158, 4 | 0x10);
195 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x054, 1 | 0x10);
196 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x13c, 4 | 0x10);
197 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x144, 4 | 0x10);
199 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x22c, 1 | 0x10);
200 HAL_WRITE_UINT32(IOMUXC_BASE_ADDR + 0x088, 4 | 0x10);
203 void plf_hardware_init(void)
209 v = (32 << 16) | /* spare area size: 32 half words */
210 (1 << 12) | /* 8bit bus */
211 (3 << 9) | /* extra dead cycles [0..7] */
212 (1 << 7) | /* PPB: 0: 32 1: 64 2: 128 3: 256 */
213 (1 << 6) | /* ECC mode: 0: 8bit 1: 4bit */
214 (0 << 5) | /* little endian */
215 (1 << 4) | /* disable interrupt */
216 (1 << 3) | /* enable ECC */
217 (0 << 2) | /* SYM: 0: asymmetric 1: symmetric */
218 (1 << 0); /* PS: 0: 512 1: 2K 2: 4K 3: 4K */
219 writel(v, NFC_FLASH_CONFIG2_REG);
221 writel(0xFFFF0000, UNLOCK_BLK_ADD0_REG);
222 writel(0xFFFF0000, UNLOCK_BLK_ADD1_REG);
223 writel(0xFFFF0000, UNLOCK_BLK_ADD2_REG);
224 writel(0xFFFF0000, UNLOCK_BLK_ADD3_REG);
226 v = NFC_WR_PROT_CS0 | NFC_WR_PROT_BLS_UNLOCK | NFC_WR_PROT_WPC;
227 writel(v, NFC_WR_PROT_REG);
229 writel(0, NFC_IPC_REG);
233 writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
234 writel(0x4, IOMUXC_BASE_ADDR + 0x604);
235 writel(0x1C5, IOMUXC_BASE_ADDR + 0x3BC);
238 writel(0x0, IOMUXC_BASE_ADDR + 0x160);
239 writel(0x1C5, IOMUXC_BASE_ADDR + 0x3C0);
242 writel(0x0, IOMUXC_BASE_ADDR + 0x164);
243 writel(0x4, IOMUXC_BASE_ADDR + 0x600);
244 writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C4);
247 writel(0x0, IOMUXC_BASE_ADDR + 0x168);
248 writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C8);
251 typedef void code_fun(void);
253 void tx37_program_new_stack(void *func)
255 register CYG_ADDRESS stack_ptr asm("sp");
256 register CYG_ADDRESS old_stack asm("r4");
257 register code_fun *new_func asm("r0");
258 old_stack = stack_ptr;
259 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
260 new_func = (code_fun*)func;
262 stack_ptr = old_stack;
265 static void display_board_info(void)
267 const char *dlm = "";
271 diag_printf("\nBoard Type: Ka-Ro TX37\n");
273 HAL_READ_UINT32(SRC_SRSR_REG, srsr);
274 diag_printf("Last RESET cause: ");
276 if (srsr & (1 << 16)) {
277 diag_printf("%s%s", dlm, "WARM BOOT");
280 if (srsr & (1 << 0)) {
281 diag_printf("%s%s", dlm, "POWER_ON");
284 if (srsr & (1 << 2)) {
285 diag_printf("%s%s", dlm, "EXTERNAL");
288 if (srsr & (1 << 3)) {
289 diag_printf("%s%s", dlm, "COLD");
292 if (srsr & (1 << 4)) {
293 HAL_READ_UINT16(WDOG_WRSR_REG, wrsr);
294 if (wrsr & (1 << 0)) {
295 diag_printf("%s%s", dlm, "SOFTWARE");
298 if (wrsr & (1 << 1)) {
299 diag_printf("%s%s", dlm, "WATCHDOG");
303 if (srsr & (1 << 5)) {
304 diag_printf("%s%s", dlm, "JTAG");
308 diag_printf("Last RESET cause: UNKNOWN: 0x%08x\n", srsr);
310 diag_printf(" RESET\n");
314 RedBoot_init(display_board_info, RedBoot_INIT_LAST);