1 #ifndef CYGONCE_HAL_MM_H
2 #define CYGONCE_HAL_MM_H
4 //=============================================================================
8 //=============================================================================
9 //####ECOSGPLCOPYRIGHTBEGIN####
10 // -------------------------------------------
11 // This file is part of eCos, the Embedded Configurable Operating System.
12 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // eCos is free software; you can redistribute it and/or modify it under
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
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31 // License. However the source code for this file must still be made available
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39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //=============================================================================
42 // -------------------------------------------------------------------------
43 // MMU initialization:
45 // These structures are laid down in memory to define the translation
50 * Translation Table Base Bit Masks
52 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
55 * Domain Access Control Bit Masks
57 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
58 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
59 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
61 struct ARM_MMU_FIRST_LEVEL_FAULT {
63 unsigned int sbz : 30;
66 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
68 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
71 unsigned int domain : 4;
73 unsigned int base_address : 23;
76 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
78 struct ARM_MMU_FIRST_LEVEL_SECTION {
83 unsigned int domain : 4;
84 unsigned int sbz0 : 1;
86 unsigned int sbz1 : 8;
87 unsigned int base_address : 12;
90 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
92 struct ARM_MMU_FIRST_LEVEL_RESERVED {
94 unsigned int sbz : 30;
97 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
99 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
100 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
102 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
104 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
105 cacheable, bufferable, perm) \
107 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
110 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
111 desc.section.domain = 0; \
112 desc.section.c = (cacheable); \
113 desc.section.b = (bufferable); \
114 desc.section.ap = (perm); \
115 desc.section.base_address = (actual_base); \
116 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
120 #define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
122 int i; int j = abase; int k = vbase; \
123 for (i = size; i > 0 ; i--,j++,k++) { \
124 ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
128 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
130 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
131 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
132 struct ARM_MMU_FIRST_LEVEL_SECTION section;
133 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
136 #define ARM_UNCACHEABLE 0
137 #define ARM_CACHEABLE 1
138 #define ARM_UNBUFFERABLE 0
139 #define ARM_BUFFERABLE 1
141 #define ARM_ACCESS_PERM_NONE_NONE 0
142 #define ARM_ACCESS_PERM_RO_NONE 0
143 #define ARM_ACCESS_PERM_RO_RO 0
144 #define ARM_ACCESS_PERM_RW_NONE 1
145 #define ARM_ACCESS_PERM_RW_RO 2
146 #define ARM_ACCESS_PERM_RW_RW 3
149 * Initialization for the Domain Access Control Register
151 #define ARM_ACCESS_DACR_DEFAULT ( \
152 ARM_ACCESS_TYPE_MANAGER(0) | \
153 ARM_ACCESS_TYPE_NO_ACCESS(1) | \
154 ARM_ACCESS_TYPE_NO_ACCESS(2) | \
155 ARM_ACCESS_TYPE_NO_ACCESS(3) | \
156 ARM_ACCESS_TYPE_NO_ACCESS(4) | \
157 ARM_ACCESS_TYPE_NO_ACCESS(5) | \
158 ARM_ACCESS_TYPE_NO_ACCESS(6) | \
159 ARM_ACCESS_TYPE_NO_ACCESS(7) | \
160 ARM_ACCESS_TYPE_NO_ACCESS(8) | \
161 ARM_ACCESS_TYPE_NO_ACCESS(9) | \
162 ARM_ACCESS_TYPE_NO_ACCESS(10) | \
163 ARM_ACCESS_TYPE_NO_ACCESS(11) | \
164 ARM_ACCESS_TYPE_NO_ACCESS(12) | \
165 ARM_ACCESS_TYPE_NO_ACCESS(13) | \
166 ARM_ACCESS_TYPE_NO_ACCESS(14) | \
167 ARM_ACCESS_TYPE_NO_ACCESS(15) )
170 * translate the virtual address of ram space to physical address
171 * It is dependent on the implementation of hal_mmu_init
173 static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
175 if (virt < 0x08000000) {
176 return virt | 0x40000000;
178 if ((virt & 0xF0000000) == 0x40000000) {
179 return virt & ~0x08000000;
185 * remap the physical address of ram space to uncacheable virtual address space
186 * It is dependent on the implementation of hal_mmu_init
188 static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
190 /* 0x48000000~0x48FFFFFF is uncacheable meory space which is mapped to SDRAM*/
191 if ((phy & 0xF0000000) == 0x40000000) {
197 // ------------------------------------------------------------------------
198 #endif // ifndef CYGONCE_HAL_MM_H