1 //==========================================================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
48 #define REG8_VAL(a) (a)
49 #define REG16_VAL(a) (a)
50 #define REG32_VAL(a) (a)
52 #define REG8_PTR(a) (a)
53 #define REG16_PTR(a) (a)
54 #define REG32_PTR(a) (a)
56 #else /* __ASSEMBLER__ */
60 extern char HAL_PLATFORM_EXTRA[];
61 #define REG8_VAL(a) ((unsigned char)(a))
62 #define REG16_VAL(a) ((unsigned short)(a))
63 #define REG32_VAL(a) ((unsigned int)(a))
65 #define REG8_PTR(a) ((volatile unsigned char *)(a))
66 #define REG16_PTR(a) ((volatile unsigned short *)(a))
67 #define REG32_PTR(a) ((volatile unsigned int *)(a))
68 #define readb(a) (*(volatile unsigned char *)(a))
69 #define readw(a) (*(volatile unsigned short *)(a))
70 #define readl(a) (*(volatile unsigned int *)(a))
71 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
72 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
73 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
75 #endif /* __ASSEMBLER__ */
78 * Default Memory Layout Definitions
81 #define L2CC_BASE_ADDR UL(0xB0000000)
83 #define IRAM_BASE_ADDR UL(0x10000000)
87 #define AIPS1_BASE_ADDR UL(0xC3F00000)
88 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
89 #define MAX_BASE_ADDR UL(0xC3F80000)
90 #define GPIO1_BASE_ADDR UL(0xC3F84000)
91 #define GPIO2_BASE_ADDR UL(0xC3F88000)
92 #define GPIO3_BASE_ADDR UL(0xC3F8C000)
93 #define KPP_BASE_ADDR UL(0xC3F94000)
94 #define WDOG1_BASE_ADDR UL(0xC3F98000)
95 #define WDOG_BASE_ADDR WDOG1_BASE_ADDR
97 #define WDOG_WCR_REG (WDOG_BASE_ADDR + 0x00)
98 #define WDOG_WRSR_REG (WDOG_BASE_ADDR + 0x04)
100 #define WDOG2_BASE_ADDR UL(0xC3F9C000)
101 #define GPT1_BASE_ADDR UL(0xC3FA0000)
102 #define RTC_BASE_ADDR UL(0xC3FA4000)
103 #define IOMUXC_BASE_ADDR UL(0xC3FA8000)
104 #define IIM_BASE_ADDR UL(0xC3FAC000)
105 #define FEC_BASE_ADDR UL(0xC3FE8000)
106 #define SOC_FEC_BASE FEC_BASE_ADDR
110 #define MMC_SDHC1_BASE_ADDR UL(0xC0004000)
111 #define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
112 #define MMC_SDHC2_BASE_ADDR UL(0xC0008000)
113 #define UART3_BASE_ADDR UL(0xC000C000)
114 #define CSPI2_BASE_ADDR UL(0xC0010000)
115 #define SSI2_BASE_ADDR UL(0xC0014000)
116 #define ATA_DMA_BASE_ADDR UL(0xC0034000)
117 #define SPBA_CTRL_BASE_ADDR UL(0xC003C000)
122 #define AIPS2_BASE_ADDR UL(0xE3F00000)
123 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
124 #define PLL1_BASE_ADDR UL(0xE3F80000)
125 #define PLL2_BASE_ADDR UL(0xE3F84000)
126 #define PLL3_BASE_ADDR UL(0xE3F88000)
127 #define CCM_BASE_ADDR UL(0xE3F8C000)
128 #define SRC_BASE_ADDR UL(0xE3F94000)
130 #define SRC_SRSR_REG (SRC_BASE_ADDR + 0x08)
132 #define EPIT1_BASE_ADDR UL(0xE3F98000)
133 #define EPIT2_BASE_ADDR UL(0xE3F9C000)
134 #define CSPI3_BASE_ADDR UL(0xE3FA8000)
135 #define CSPI1_BASE_ADDR UL(0xE3FAC000)
136 #define UART1_BASE_ADDR UL(0xE3FB0000)
137 #define UART2_BASE_ADDR UL(0xE3FBC000)
138 #define I2C3_BASE_ADDR UL(0xE3FC0000)
139 #define I2C2_BASE_ADDR UL(0xE3FC4000)
140 #define I2C_BASE_ADDR UL(0xE3FC8000)
141 #define SSI1_BASE_ADDR UL(0xE3FCC000)
142 #define AUDMUX_BASE UL(0xE3FD0000)
144 #define GPC_BASE_ADDR UL(0xE3F90000)
145 #define GPC_CNTR_REG (GPC_BASE_ADDR + 0x0)
146 #define GPC_PGR_REG (GPC_BASE_ADDR + 0x4)
147 #define GPC_VCR_REG (GPC_BASE_ADDR + 0x8)
149 #define PGC_BASE_VPU (GPC_BASE_ADDR + 0x0240)
150 #define PGC_BASE_IPU (GPC_BASE_ADDR + 0x0220)
151 #define GPC_PGR (GPC_BASE_ADDR + 0x000)
152 #define SRPGCR_ARM (GPC_BASE_ADDR + 0x02A0 + 0x0000)
153 #define SRPGCR_EMI (GPC_BASE_ADDR + 0x0280 + 0x0000)
154 #define PGC_PGCR_VPU (PGC_BASE_VPU + 0x0000)
155 #define PGC_PGCR_IPU (PGC_BASE_IPU + 0x0000)
157 #define PLATFORM_BASE_ADDR UL(0xB0404000)
158 #define PLATFORM_LPC_REG (PLATFORM_BASE_ADDR + 0x14)
161 * Interrupt controller
163 #define INTC_BASE_ADDR UL(0xB0800000)
166 * NAND, SDRAM, WEIM, M4IF, EMI controllers
168 #define NFC_IP_BASE UL(0xE3FDB000)
169 #define ESDCTL_BASE UL(0xE3FD9000)
170 #define WEIM_BASE_ADDR UL(0xE3FDA000)
172 #define WEIM_CTRL_CS0 WEIM_BASE_ADDR
173 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x18)
174 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x30)
175 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x48)
176 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x60)
177 #define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x78)
178 #define M4IF_BASE UL(0xE3FD8000)
181 * Memory regions and CS
183 #define CSD0_BASE_ADDR UL(0x40000000)
184 #define CSD1_BASE_ADDR UL(0x50000000)
185 #define CS0_BASE_ADDR UL(0x60000000)
186 #define CS1_BASE_ADDR UL(0x68000000)
187 #define CS2_BASE_ADDR UL(0x70000000)
190 * IRQ Controller Register Definitions.
192 #define INTC_NIMASK REG32_PTR(INTC_BASE_ADDR + (0x04))
193 #define INTC_INTTYPEH REG32_PTR(INTC_BASE_ADDR + (0x18))
194 #define INTC_INTTYPEL REG32_PTR(INTC_BASE_ADDR + (0x1C))
197 #define M4IF_FBPM0 0x40
198 #define M4IF_FIDBP 0x48
201 #define L2_CACHE_LINE_SIZE 32
202 #define L2_CACHE_CTL_REG 0x100
203 #define L2_CACHE_AUX_CTL_REG 0x104
204 #define L2_CACHE_SYNC_REG 0x730
205 #define L2_CACHE_INV_LINE_REG 0x770
206 #define L2_CACHE_INV_WAY_REG 0x77C
207 #define L2_CACHE_CLEAN_LINE_PA_REG 0x7B0
208 #define L2_CACHE_CLEAN_LINE_WAY_REG 0x7B8
209 #define L2_CACHE_CLEAN_WAY_REG 0x7BC
210 #define L2_CACHE_CLEAN_INV_LINE_PA_REG 0x7F0
211 #define L2_CACHE_CLEAN_INV_LINE_WAY_REG 0x7F8
212 #define L2_CACHE_CLEAN_INV_WAY_REG 0x7FC
215 #define CLKCTL_CCMR 0x00
216 #define CLKCTL_PDR0 0x04
217 #define CLKCTL_PDR1 0x08
219 #define CLKCTL_CCSR 0x0C
220 #define CLKCTL_CACRR 0x10
221 #define CLKCTL_CBCDR2 0x18
222 #define CLKCTL_CBCDR3 0x1C
223 #define CLKCTL_CBCDR4 0x20
224 #define CLKCTL_CBCDR5 0x24
225 #define CLKCTL_CBCDR6 0x28
226 #define CLKCTL_CBCDR7 0x2C
227 #define CLKCTL_CAMR 0x30
228 #define CLKCTL_PDR2 0x64
229 #define CLKCTL_RCSR 0x0C
230 #define CLKCTL_MPCTL 0x10
231 #define CLKCTL_UPCTL 0x14
232 #define CLKCTL_SPCTL 0x18
233 #define CLKCTL_COSR 0x1C
234 #define CLKCTL_CSCMR1 0x34
235 #define CLKCTL_CSCDR1 0x3C
236 #define CLKCTL_CS1CDR 0x40
237 #define CLKCTL_CS2CDR 0x44
238 #define CLKCTL_CSCDR2 0x60
239 #define CLKCTL_CDCR 0x6C
240 #define CLKCTL_CCOSR 0x80
242 #define FREQ_24MHZ 24000000
243 #define FREQ_32768HZ (32768 * 1024)
244 #define FREQ_38400HZ (38400 * 1024)
245 #define FREQ_32000HZ (32000 * 1024)
246 #define PLL_REF_CLK FREQ_24MHZ
247 //#define PLL_REF_CLK FREQ_32768HZ
248 //#define PLL_REF_CLK FREQ_32000HZ
258 #define ESDCTL_ESDCTL0 0x00
259 #define ESDCTL_ESDCFG0 0x04
260 #define ESDCTL_ESDCTL1 0x08
261 #define ESDCTL_ESDCFG1 0x0C
262 #define ESDCTL_ESDMISC 0x10
263 #define ESDCTL_ESDSCR 0x14
264 #define ESDCTL_ESDCDLY1 0x20
265 #define ESDCTL_ESDCDLY2 0x24
266 #define ESDCTL_ESDCDLY3 0x28
267 #define ESDCTL_ESDCDLY4 0x2C
268 #define ESDCTL_ESDCDLY5 0x30
269 #define ESDCTL_ESDCDLYGD 0x34
272 #define PLL_DP_CTL 0x00
273 #define PLL_DP_CONFIG 0x04
274 #define PLL_DP_OP 0x08
275 #define PLL_DP_MFD 0x0C
276 #define PLL_DP_MFN 0x10
277 #define PLL_DP_MFNMINUS 0x14
278 #define PLL_DP_MFNPLUS 0x18
279 #define PLL_DP_HFS_OP 0x1C
280 #define PLL_DP_HFS_MFD 0x20
281 #define PLL_DP_HFS_MFN 0x24
282 #define PLL_DP_TOGC 0x28
283 #define PLL_DP_DESTAT 0x2C
285 #define CHIP_REV_1_0 0x0 /* PASS 1.0 */
286 #define CHIP_REV_1_1 0x1 /* PASS 1.1 */
287 #define CHIP_REV_2_0 0x2 /* PASS 2.0 */
288 #define CHIP_LATEST CHIP_REV_1_1
290 #define IIM_STAT_OFF 0x00
291 #define IIM_STAT_BUSY (1 << 7)
292 #define IIM_STAT_PRGD (1 << 1)
293 #define IIM_STAT_SNSD (1 << 0)
294 #define IIM_STATM_OFF 0x04
295 #define IIM_ERR_OFF 0x08
296 #define IIM_ERR_PRGE (1 << 7)
297 #define IIM_ERR_WPE (1 << 6)
298 #define IIM_ERR_OPE (1 << 5)
299 #define IIM_ERR_RPE (1 << 4)
300 #define IIM_ERR_WLRE (1 << 3)
301 #define IIM_ERR_SNSE (1 << 2)
302 #define IIM_ERR_PARITYE (1 << 1)
303 #define IIM_EMASK_OFF 0x0C
304 #define IIM_FCTL_OFF 0x10
305 #define IIM_UA_OFF 0x14
306 #define IIM_LA_OFF 0x18
307 #define IIM_SDAT_OFF 0x1C
308 #define IIM_PREV_OFF 0x20
309 #define IIM_SREV_OFF 0x24
310 #define IIM_PREG_P_OFF 0x28
311 #define IIM_SCS0_OFF 0x2C
312 #define IIM_SCS1_P_OFF 0x30
313 #define IIM_SCS2_OFF 0x34
314 #define IIM_SCS3_P_OFF 0x38
316 #define EPIT_BASE_ADDR EPIT1_BASE_ADDR
320 #define EPITCMPR 0x0C
323 /*defines iomux for mx37*/
324 #define IOMUX_SD1_CMD_PORT 0
325 #define IOMUX_SD1_CMD_PIN 32
326 #define IOMUX_SD1_CMD_SEL (0x200 | 0x10 | (51 << 12))
327 #define IOMUX_SD1_CMD_DIR 0xFF
329 #define IOMUX_SD1_CLK_PORT 0
330 #define IOMUX_SD1_CLK_PIN 32
331 #define IOMUX_SD1_CLK_SEL (0x200 | (52 << 12))
332 #define IOMUX_SD1_CLK_DIR 0xFF
334 #define IOMUX_SD1_DATA0_PORT 0
335 #define IOMUX_SD1_DATA0_PIN 32
336 #define IOMUX_SD1_DATA0_SEL (0x200 | (53 << 12))
337 #define IOMUX_SD1_DATA0_DIR 0xFF
339 #define IOMUX_SD1_DATA1_PORT 0
340 #define IOMUX_SD1_DATA1_PIN 32
341 #define IOMUX_SD1_DATA1_SEL (0x200 | (54 << 12))
342 #define IOMUX_SD1_DATA1_DIR 0xFF
344 #define IOMUX_SD1_DATA2_PORT 0
345 #define IOMUX_SD1_DATA2_PIN 32
346 #define IOMUX_SD1_DATA2_SEL (0x200 | (55 << 12))
347 #define IOMUX_SD1_DATA2_DIR 0xFF
349 #define IOMUX_SD1_DATA3_PORT 0
350 #define IOMUX_SD1_DATA3_PIN 32
351 #define IOMUX_SD1_DATA3_SEL (0x200 | (56 << 12))
352 #define IOMUX_SD1_DATA3_DIR 0xFF
354 #define IOMUX_SD2_DATA0_PORT 0
355 #define IOMUX_SD2_DATA0_PIN 32
356 #define IOMUX_SD2_DATA0_SEL (0x200 | 0x4 | (59 << 12))
357 #define IOMUX_SD2_DATA0_DIR 0xFF
358 #define IOMUX_SD2_DATA1_PORT 0
359 #define IOMUX_SD2_DATA1_PIN 32
360 #define IOMUX_SD2_DATA1_SEL (0x200 | 0x4 | (60 << 12))
361 #define IOMUX_SD2_DATA1_DIR 0xFF
362 #define IOMUX_SD2_DATA2_PORT 0
363 #define IOMUX_SD2_DATA2_PIN 32
364 #define IOMUX_SD2_DATA2_SEL (0x200 | 0x4 | (61 << 12))
365 #define IOMUX_SD2_DATA2_DIR 0xFF
366 #define IOMUX_SD2_DATA3_PORT 0
367 #define IOMUX_SD2_DATA3_PIN 32
368 #define IOMUX_SD2_DATA3_SEL (0x200 | 0x4 | (62 << 12))
369 #define IOMUX_SD2_DATA3_DIR 0xFF
371 #define IOMUX_PAD_GPIO1_4_PORT 0
372 #define IOMUX_PAD_GPIO1_4_PIN 32
373 #define IOMUX_PAD_GPIO1_4_SEL (0x200 | 0x6 | (134 << 12))
374 #define IOMUX_PAD_GPIO1_4_SEL_1 (0x200 | 0x0 | (134 << 12))
375 #define IOMUX_PAD_GPIO1_4_DIR 0xFF
377 #define IOMUX_PAD_GPIO1_5_PORT 0
378 #define IOMUX_PAD_GPIO1_5_PIN 32
379 #define IOMUX_PAD_GPIO1_5_SEL (0x200 | 0x6 | (135 << 12))
380 #define IOMUX_PAD_GPIO1_5_DIR 0xFF
382 #define IOMUX_PAD_GPIO1_6_PORT 0
383 #define IOMUX_PAD_GPIO1_6_PIN 32
384 #define IOMUX_PAD_GPIO1_6_SEL (0x200 | 0x6 | (136 << 12))
385 #define IOMUX_PAD_GPIO1_6_DIR 0xFF
387 #define GPT_BASE_ADDR GPT1_BASE_ADDR
399 /* Assuming 26MHz input clock */
401 #define MPCTL_PARAM_208 (((2-1) << 26) + ((1 -1) << 16) + (8 << 10) + (0 << 0))
402 #define MPCTL_PARAM_399 (((1-1) << 26) + ((52-1) << 16) + (7 << 10) + (35 << 0))
403 #define MPCTL_PARAM_532 (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
404 #define MPCTL_PARAM_665 (((1-1) << 26) + ((52-1) << 16) + (12 << 10) + (41 << 0))
405 #define MPCTL_PARAM_532_27 (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
407 /* UPCTL PD MFD MFI MFN */
408 #define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
409 #define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
410 #define UPCTL_PARAM_240_27 (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
413 #define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
414 #define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
415 #define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
416 #define PDR0_532_133_66 0xFF871D58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
417 #define PDR0_665_83_42 0xFF873B78 /* ARM=665MHz, HCLK=83MHz, IPG=42MHz */
418 #define PDR0_665_133_66 0xFF872560 /* ARM=665MHz, HCLK=133MHz, IPG=66MHz */
420 //#define BARKER_CODE_SWAP_LOC 0x404
421 #define BARKER_CODE_VAL 0xB1
423 #define NFC_BASE UL(0x7FFF0000)
424 #define NAND_REG_BASE (NFC_BASE + 0x1E00)
426 #define NAND_ADD_CMD_REG (NAND_REG_BASE + 0x00)
428 #define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x04)
429 #define NAND_CONFIGURATION1_NFC_RST (1 << 2)
430 #define NAND_CONFIGURATION1_NF_CE (1 << 1)
431 #define NAND_CONFIGURATION1_SP_EN (1 << 0)
433 #define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x08)
435 #define NAND_LAUNCH_REG (NAND_REG_BASE + 0x0C)
436 #define NAND_LAUNCH_FCMD (1 << 0)
437 #define NAND_LAUNCH_FADD (1 << 1)
438 #define NAND_LAUNCH_FDI (1 << 2)
441 #define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
442 #define NFC_WR_PROT_CS0 (0 << 20)
443 #define NFC_WR_PROT_BLS_UNLOCK (2 << 16)
444 #define NFC_WR_PROT_WPC (4 << 0)
446 #define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
448 #define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
450 #define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
452 #define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
454 #define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x14)
455 #define NFC_FLASH_CONFIG2_EDC0 (0 << 9)
456 #define NFC_FLASH_CONFIG2_EDC1 (1 << 9)
457 #define NFC_FLASH_CONFIG2_EDC2 (2 << 9)
458 #define NFC_FLASH_CONFIG2_EDC3 (3 << 9)
459 #define NFC_FLASH_CONFIG2_EDC4 (4 << 9)
460 #define NFC_FLASH_CONFIG2_EDC5 (5 << 9)
461 #define NFC_FLASH_CONFIG2_EDC6 (6 << 9)
462 #define NFC_FLASH_CONFIG2_EDC7 (7 << 9)
463 #define NFC_FLASH_CONFIG2_PPB_32 (0 << 7)
464 #define NFC_FLASH_CONFIG2_PPB_64 (1 << 7)
465 #define NFC_FLASH_CONFIG2_PPB_128 (2 << 7)
466 #define NFC_FLASH_CONFIG2_PPB_256 (3 << 7)
467 #define NFC_FLASH_CONFIG2_INT_MSK (1 << 4)
468 #define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
469 #define NFC_FLASH_CONFIG2_SYM (1 << 2)
471 #define NFC_IPC_REG (NFC_IP_BASE + 0x18)
472 #define NFC_IPC_INT (1 << 31)
473 #define NFC_IPC_LPS (1 << 30)
474 #define NFC_IPC_RB_B (1 << 29)
475 #define NFC_IPC_CACK (1 << 1)
476 #define NFC_IPC_CREQ (1 << 0)
477 #define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x1C)
479 #define MXC_NAND_BASE_DUMMY 0x00000000
480 #define MXC_MMC_BASE_DUMMY 0x00000000
482 #define FROM_SDRAM 0x00000000
483 #define FROM_NAND_FLASH 0x10000000
484 #define FROM_NOR_FLASH 0x20000000
485 #define FROM_MMC_FLASH 0x40000000
486 #define FROM_SPI_NOR_FLASH 0x80000000
488 #define IS_BOOTING_FROM_NAND() (_mxc_boot == FROM_NAND_FLASH)
489 // No NOR flash is supported under MX37 for booting
490 #define IS_BOOTING_FROM_NOR() 0
491 #define IS_BOOTING_FROM_SPI_NOR() 0
492 #define IS_BOOTING_FROM_SDRAM() (_mxc_boot == FROM_SDRAM)
493 #define IS_BOOTING_FROM_MMC() (_mxc_boot == FROM_MMC_FLASH)
495 #ifndef MXCFLASH_SELECT_NAND
496 #define IS_FIS_FROM_NAND() 0
498 #define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH)
501 #ifndef MXCFLASH_SELECT_MMC
502 #define IS_FIS_FROM_MMC() 0
504 #define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH)
507 #define IS_FIS_FROM_NOR() 0
510 * This macro is used to get certain bit field from a number
512 #define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
515 * This macro is used to set certain bit field inside a number
517 #define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
520 #define UART_WIDTH_32 /* internal UART is 32bit access only */
522 /* Offsets for system_rev */
523 #define PART_NUMBER_OFFSET 12
524 #define PMIC_ID_OFFSET 8
525 #define MAJOR_NUMBER_OFFSET 4
526 #define MINOR_NUMBER_OFFSET 0
528 #if !defined(__ASSEMBLER__)
529 void cyg_hal_plf_serial_init(void);
530 void cyg_hal_plf_serial_stop(void);
531 void hal_delay_us(unsigned int usecs);
532 #define HAL_DELAY_US(n) hal_delay_us(n)
534 extern int _mxc_boot;
535 extern unsigned int system_rev;
562 SPI1_CLK = CSPI1_BASE_ADDR,
563 SPI2_CLK = CSPI2_BASE_ADDR,
566 unsigned int pll_clock(enum plls pll);
568 unsigned int get_main_clock(enum main_clocks clk);
570 unsigned int get_peri_clock(enum peri_clocks clk);
572 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
574 #endif //#if !defined(__ASSEMBLER__)
576 #define HAL_MMU_OFF() \
579 "mcr p15, 0, r0, c7, c14, 0;" \
580 "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
581 "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I cache */ \
582 "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
583 "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
584 "bic r0, r0, #0x1000;" /* disable ICache */ \
585 "mcr p15, 0, r0, c1, c0, 0;" \
586 "nop;" /* flush i+d-TLBs */ \
587 "nop;" /* flush i+d-TLBs */ \
588 "nop;" /* flush i+d-TLBs */ \
591 : "r0","memory" /* clobber list */); \
594 #endif /* __HAL_SOC_H__ */