1 //==========================================================================
5 // HAL misc board support code for the board
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
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34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
42 #include <pkgconf/hal.h>
43 #include <pkgconf/system.h>
45 #include CYGBLD_HAL_PLATFORM_H
47 #include <cyg/infra/cyg_type.h> // base types
48 #include <cyg/infra/cyg_trac.h> // tracing macros
49 #include <cyg/infra/cyg_ass.h> // assertion macros
51 #include <cyg/hal/hal_io.h> // IO macros
52 #include <cyg/hal/hal_arch.h> // Register state info
53 #include <cyg/hal/hal_diag.h>
54 #include <cyg/hal/hal_intr.h> // Interrupt names
55 #include <cyg/hal/hal_cache.h>
56 #include <cyg/hal/hal_soc.h> // Hardware definitions
57 #include <cyg/hal/fsl_board.h> // Platform specifics
58 #include <cyg/io/mxc_i2c.h>
59 #include <cyg/io/imx_nfc.h>
60 #include <cyg/infra/diag.h> // diag_printf
62 // All the MM table layout is here:
63 #include <cyg/hal/hal_mm.h>
65 externC void* memset(void *, int, size_t);
66 extern nfc_iomuxsetup_func_t *nfc_iomux_setup;
68 unsigned int cpld_base_addr;
70 void hal_mmu_init(void)
72 unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
76 * Set the TTB register
78 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
81 * Set the Domain Access Control Register
83 i = ARM_ACCESS_DACR_DEFAULT;
84 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
87 * First clear all TT entries - ie Set them to Faulting
89 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
91 /* Actual Virtual Size Attributes Function */
92 /* Base Base MB cached? buffered? access permissions */
93 /* xxx00000 xxx00000 */
94 X_ARM_MMU_SECTION(0x000, 0x200, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
95 X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
96 X_ARM_MMU_SECTION(0x300, 0x300, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* GPU */
97 X_ARM_MMU_SECTION(0x400, 0x400, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
98 X_ARM_MMU_SECTION(0x600, 0x600, 0x300, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */
99 X_ARM_MMU_SECTION(0x900, 0x000, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
100 X_ARM_MMU_SECTION(0x900, 0x900, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
101 X_ARM_MMU_SECTION(0x900, 0x980, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
102 X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
103 X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
106 void mxc_i2c_init(unsigned int module_base)
110 switch (module_base) {
112 if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
113 reg = IOMUXC_BASE_ADDR + 0x210; // i2c SDA
115 reg = IOMUXC_BASE_ADDR + 0x600;
117 reg = IOMUXC_BASE_ADDR + 0x9B4;
120 reg = IOMUXC_BASE_ADDR + 0x224; // i2c SCL
122 reg = IOMUXC_BASE_ADDR + 0x614;
124 reg = IOMUXC_BASE_ADDR + 0x9B0;
127 reg = IOMUXC_BASE_ADDR + 0x230; // i2c SCL
129 reg = IOMUXC_BASE_ADDR + 0x6e0;
131 reg = IOMUXC_BASE_ADDR + 0xA00;
134 reg = IOMUXC_BASE_ADDR + 0x21C; // i2c SDA
136 reg = IOMUXC_BASE_ADDR + 0x6cc;
138 reg = IOMUXC_BASE_ADDR + 0xA04;
143 if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
144 /* Workaround for Atlas Lite */
145 writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
146 writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
147 reg = readl(GPIO1_BASE_ADDR + 0x0);
148 reg |= 0xC; // write a 1 on the SCL and SDA lines
149 writel(reg, GPIO1_BASE_ADDR + 0x0);
150 reg = readl(GPIO1_BASE_ADDR + 0x4);
151 reg |= 0xC; // configure GPIO lines as output
152 writel(reg, GPIO1_BASE_ADDR + 0x4);
153 reg = readl(GPIO1_BASE_ADDR + 0x0);
154 reg &= ~0x4 ; // set SCL low for a few milliseconds
155 writel(reg, GPIO1_BASE_ADDR + 0x0);
158 writel(reg, GPIO1_BASE_ADDR + 0x0);
160 reg = readl(GPIO1_BASE_ADDR + 0x4);
161 reg &= ~0xC; // configure GPIO lines back as input
162 writel(reg, GPIO1_BASE_ADDR + 0x4);
164 writel(0x12, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
165 writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
166 writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
168 writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
169 writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
170 writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
172 /* Workaround for Atlas Lite */
173 writel(0x0, IOMUXC_BASE_ADDR + 0x3D4); // i2c SCL
174 writel(0x0, IOMUXC_BASE_ADDR + 0x3D8); // i2c SDA
175 reg = readl(GPIO1_BASE_ADDR + 0x0);
176 reg |= 0xC; // write a 1 on the SCL and SDA lines
177 writel(reg, GPIO1_BASE_ADDR + 0x0);
178 reg = readl(GPIO1_BASE_ADDR + 0x4);
179 reg |= 0xC; // configure GPIO lines as output
180 writel(reg, GPIO1_BASE_ADDR + 0x4);
181 reg = readl(GPIO1_BASE_ADDR + 0x0);
182 reg &= ~0x4 ; // set SCL low for a few milliseconds
183 writel(reg, GPIO1_BASE_ADDR + 0x0);
186 writel(reg, GPIO1_BASE_ADDR + 0x0);
188 reg = readl(GPIO1_BASE_ADDR + 0x4);
189 reg &= ~0xC; // configure GPIO lines back as input
190 writel(reg, GPIO1_BASE_ADDR + 0x4);
192 writel(0x12, IOMUXC_BASE_ADDR + 0x3D4); // i2c SCL
193 writel(0x3, IOMUXC_BASE_ADDR + 0xA08);
194 writel(0x1ed, IOMUXC_BASE_ADDR + 0x8A0);
196 writel(0x12, IOMUXC_BASE_ADDR + 0x3D8); // i2c SDA
197 writel(0x3, IOMUXC_BASE_ADDR + 0xA0C);
198 writel(0x1ed, IOMUXC_BASE_ADDR + 0x8A4);
202 diag_printf("Invalid I2C base: 0x%x\n", module_base);
207 void mxc_ata_iomux_setup(void)
209 // config NANDF_WE_B pad for pata instance DIOW port
210 // config_pad_mode(NANDF_WE_B, ALT1);
211 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B);
212 // CONSTANT SETTINGS:
213 // test_ts to Disabled
214 // dse test to regular
215 // strength mode to NA (Different from Module Level value: 4_level)
216 // DDR / CMOS Input Mode to NA
217 // Pull / Keep Select to Pull (Different from Module Level value: NA)
218 // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
219 // Open Drain Enable to Disabled
221 // CONFIGURED SETTINGS:
222 // low/high output voltage to CFG(High)
223 // Hyst. Enable to Disabled
224 // Pull / Keep Enable to Disabled
225 // Drive Strength to CFG(High)
226 // config_pad_settings(NANDF_WE_B, 0x2004);
227 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B);
229 // config NANDF_RE_B pad for pata instance DIOR port
230 // config_pad_mode(NANDF_RE_B, ALT1);
231 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B);
232 // CONSTANT SETTINGS:
233 // test_ts to Disabled
234 // dse test to regular
235 // strength mode to NA (Different from Module Level value: 4_level)
236 // DDR / CMOS Input Mode to NA
237 // Pull / Keep Select to Pull (Different from Module Level value: NA)
238 // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
239 // Open Drain Enable to Disabled
241 // CONFIGURED SETTINGS:
242 // low/high output voltage to CFG(High)
243 // Hyst. Enable to Disabled
244 // Pull / Keep Enable to Disabled
245 // Drive Strength to CFG(High)
246 // config_pad_settings(NANDF_RE_B, 0x2004);
247 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B);
249 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE);
250 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE);
252 // config NANDF_CLE pad for pata instance PATA_RESET_B port
253 // config_pad_mode(NANDF_CLE, ALT1);
254 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE);
255 // CONSTANT SETTINGS:
256 // test_ts to Disabled
257 // dse test to regular
258 // strength mode to NA (Different from Module Level value: 4_level)
259 // DDR / CMOS Input Mode to NA
260 // Hyst. Enable to Disabled
261 // Pull / Keep Select to Keep (Different from Module Level value: NA)
262 // Pull Up / Down Config. to 100Kohm PU (Different from Module Level value: NA)
263 // Open Drain Enable to Disabled
265 // CONFIGURED SETTINGS:
266 // low/high output voltage to CFG(High)
267 // Pull / Keep Enable to Disabled
268 // Drive Strength to CFG(High)
269 // config_pad_settings(NANDF_CLE, 0x2004);
270 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE);
272 // config NANDF_WP_B pad for pata instance DMACK port
273 // config_pad_mode(NANDF_WP_B, ALT1);
274 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B);
275 // CONSTANT SETTINGS:
276 // test_ts to Disabled
277 // dse test to regular
278 // strength mode to NA (Different from Module Level value: 4_level)
279 // DDR / CMOS Input Mode to NA
280 // Pull / Keep Select to Pull (Different from Module Level value: NA)
281 // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
282 // Open Drain Enable to Disabled
284 // CONFIGURED SETTINGS:
285 // low/high output voltage to CFG(High)
286 // Hyst. Enable to Disabled
287 // Pull / Keep Enable to Disabled
288 // Drive Strength to CFG(High)
289 // config_pad_settings(NANDF_WP_B, 0x2004);
290 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B);
292 // config NANDF_RB0 pad for pata instance DMARQ port
293 // config_pad_mode(NANDF_RB0, 0x1);
294 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0);
295 // CONSTANT SETTINGS:
296 // test_ts to Disabled
297 // dse test to regular
298 // strength mode to NA (Different from Module Level value: 4_level)
299 // DDR / CMOS Input Mode to NA
300 // Open Drain Enable to Disabled (Different from Module Level value: NA)
301 // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
303 // CONFIGURED SETTINGS:
304 // low/high output voltage to CFG(High)
305 // Hyst. Enable to Disabled
306 // Pull / Keep Enable to CFG(Enabled)
307 // Pull / Keep Select to Pull
308 // Pull Up / Down Config. to CFG(360Kohm PD)
309 // config_pad_settings(NANDF_RB0, 0x20c0);
310 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0);
312 // config NANDF_RB1 pad for pata instance IORDY port
313 // config_pad_mode(NANDF_RB1, 0x1);
314 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1);
315 // CONSTANT SETTINGS:
316 // test_ts to Disabled
317 // dse test to regular
318 // strength mode to NA (Different from Module Level value: 4_level)
319 // DDR / CMOS Input Mode to NA
320 // Open Drain Enable to NA (CFG in SoC Level however NA in Module Level)
321 // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
323 // CONFIGURED SETTINGS:
324 // low/high output voltage to CFG(High)
325 // Hyst. Enable to Disabled
326 // Pull / Keep Enable to CFG(Enabled)
327 // Pull / Keep Select to Pull
328 // Pull Up / Down Config. to 100Kohm PU
329 // config_pad_settings(NANDF_RB1, 0x20e0);
330 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1);
332 // config NANDF_RB5 pad for pata instance INTRQ port
333 // config_pad_mode(NANDF_RB5, 0x1);
334 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB5);
335 // CONSTANT SETTINGS:
336 // test_ts to Disabled
337 // dse test to regular
338 // strength mode to NA (Different from Module Level value: 4_level)
339 // DDR / CMOS Input Mode to NA
340 // Pull Up / Down Config. to 100Kohm PU
341 // Open Drain Enable to Disabled (Different from Module Level value: NA)
342 // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
344 // CONFIGURED SETTINGS:
345 // low/high output voltage to CFG(High)
346 // Hyst. Enable to Disabled
347 // Pull / Keep Enable to CFG(Enabled)
348 // Pull / Keep Select to Pull
349 // config_pad_settings(NANDF_RB5, 0x20c0);
350 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5);
352 // config NANDF_CS2 pad for pata instance CS_0 port
353 // config_pad_mode(NANDF_CS2, 0x1);
354 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2);
355 // CONSTANT SETTINGS:
356 // test_ts to Disabled
357 // dse test to regular
358 // strength mode to NA (Different from Module Level value: 4_level)
359 // DDR / CMOS Input Mode to NA
360 // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
361 // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
363 // CONFIGURED SETTINGS:
364 // low/high output voltage to CFG(High)
365 // Hyst. Enable to Disabled
366 // Pull / Keep Enable to Disabled
367 // Open Drain Enable to Disabled
368 // Drive Strength to CFG(High)
369 // config_pad_settings(NANDF_CS2, 0x2004);
370 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2);
372 // config NANDF_CS3 pad for pata instance CS_1 port
373 // config_pad_mode(NANDF_CS3, 0x1);
374 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3);
375 // CONSTANT SETTINGS:
376 // test_ts to Disabled
377 // dse test to regular
378 // strength mode to NA (Different from Module Level value: 4_level)
379 // DDR / CMOS Input Mode to NA
380 // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
381 // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
383 // CONFIGURED SETTINGS:
384 // low/high output voltage to CFG(High)
385 // Hyst. Enable to Disabled
386 // Pull / Keep Enable to Disabled
387 // Open Drain Enable to Disabled
388 // Drive Strength to CFG(High)
389 // config_pad_settings(NANDF_CS3, 0x2004);
390 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3);
392 // config NANDF_CS4 pad for pata instance DA_0 port
393 // config_pad_mode(NANDF_CS4, 0x1);
394 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4);
395 // CONSTANT SETTINGS:
396 // test_ts to Disabled
397 // dse test to regular
398 // strength mode to NA (Different from Module Level value: 4_level)
399 // DDR / CMOS Input Mode to NA
400 // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
401 // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
402 // Open Drain Enable to Disabled
404 // CONFIGURED SETTINGS:
405 // low/high output voltage to CFG(High)
406 // Hyst. Enable to Disabled
407 // Pull / Keep Enable to Disabled
408 // Drive Strength to CFG(High)
409 // config_pad_settings(NANDF_CS4, 0x2004);
410 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4);
412 // config NANDF_CS5 pad for pata instance DA_1 port
413 // config_pad_mode(NANDF_CS5, 0x1);
414 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5);
415 // CONSTANT SETTINGS:
416 // test_ts to Disabled
417 // dse test to regular
418 // strength mode to NA (Different from Module Level value: 4_level)
419 // DDR / CMOS Input Mode to NA
420 // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
421 // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
422 // Open Drain Enable to Disabled
424 // CONFIGURED SETTINGS:
425 // low/high output voltage to CFG(High)
426 // Hyst. Enable to Disabled
427 // Pull / Keep Enable to Disabled
428 // Drive Strength to CFG(High)
429 // config_pad_settings(NANDF_CS5, 0x2004);
430 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5);
432 // config NANDF_CS6 pad for pata instance DA_2 port
433 // config_pad_mode(NANDF_CS6, 0x1);
434 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6);
435 // CONSTANT SETTINGS:
436 // test_ts to Disabled
437 // dse test to regular
438 // strength mode to NA (Different from Module Level value: 4_level)
439 // DDR / CMOS Input Mode to NA
440 // Pull / Keep Select to Pull (Different from Module Level value: NA)
441 // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
442 // Open Drain Enable to Disabled
444 // CONFIGURED SETTINGS:
445 // low/high output voltage to CFG(High)
446 // Hyst. Enable to Disabled
447 // Pull / Keep Enable to Disabled
448 // Drive Strength to CFG(High)
449 // config_pad_settings(NANDF_CS6, 0x2004);
450 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6);
452 // config NANDF_D15 pad for pata instance PATA_DATA[15] port
453 // config_pad_mode(NANDF_D15, 0x1);
454 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D15);
455 // CONSTANT SETTINGS:
456 // test_ts to Disabled
457 // dse test to regular
458 // strength mode to NA (Different from Module Level value: 4_level)
459 // DDR / CMOS Input Mode to NA
460 // Open Drain Enable to Disabled
462 // CONFIGURED SETTINGS:
463 // low/high output voltage to CFG(High)
464 // Hyst. Enable to Disabled
465 // Pull / Keep Enable to CFG(Enabled)
466 // Pull / Keep Select to Pull
467 // Pull Up / Down Config. to 100Kohm PU
468 // Drive Strength to CFG(High)
469 // config_pad_settings(NANDF_D15, 0x2004);
470 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D15);
472 // config NANDF_D14 pad for pata instance PATA_DATA[14] port
473 // config_pad_mode(NANDF_D14, 0x1);
474 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D14);
475 // CONSTANT SETTINGS:
476 // test_ts to Disabled
477 // dse test to regular
478 // strength mode to NA (Different from Module Level value: 4_level)
479 // DDR / CMOS Input Mode to NA
480 // Open Drain Enable to Disabled
482 // CONFIGURED SETTINGS:
483 // low/high output voltage to CFG(High)
484 // Hyst. Enable to Disabled
485 // Pull / Keep Enable to CFG(Enabled)
486 // Pull / Keep Select to Pull
487 // Pull Up / Down Config. to 100Kohm PU
488 // Drive Strength to CFG(High)
489 // config_pad_settings(NANDF_D14, 0x2004);
490 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D14);
492 // config NANDF_D13 pad for pata instance PATA_DATA[13] port
493 // config_pad_mode(NANDF_D13, 0x1);
494 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D13);
495 // CONSTANT SETTINGS:
496 // test_ts to Disabled
497 // dse test to regular
498 // strength mode to NA (Different from Module Level value: 4_level)
499 // DDR / CMOS Input Mode to NA
500 // Open Drain Enable to Disabled
502 // CONFIGURED SETTINGS:
503 // low/high output voltage to CFG(High)
504 // Hyst. Enable to Disabled
505 // Pull / Keep Enable to CFG(Enabled)
506 // Pull / Keep Select to Pull
507 // Pull Up / Down Config. to 100Kohm PU
508 // Drive Strength to CFG(High)
509 // config_pad_settings(NANDF_D13, 0x2004);
510 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D13);
512 // config NANDF_D12 pad for pata instance PATA_DATA[12] port
513 // config_pad_mode(NANDF_D12, 0x1);
514 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D12);
515 // CONSTANT SETTINGS:
516 // test_ts to Disabled
517 // dse test to regular
518 // strength mode to NA (Different from Module Level value: 4_level)
519 // DDR / CMOS Input Mode to NA
520 // Open Drain Enable to Disabled
522 // CONFIGURED SETTINGS:
523 // low/high output voltage to CFG(High)
524 // Hyst. Enable to Disabled
525 // Pull / Keep Enable to CFG(Enabled)
526 // Pull / Keep Select to Pull
527 // Pull Up / Down Config. to 100Kohm PU
528 // Drive Strength to CFG(High)
529 // config_pad_settings(NANDF_D12, 0x2004);
530 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D12);
532 // config NANDF_D11 pad for pata instance PATA_DATA[11] port
533 // config_pad_mode(NANDF_D11, 0x1);
534 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D11);
535 // CONSTANT SETTINGS:
536 // test_ts to Disabled
537 // dse test to regular
538 // strength mode to NA (Different from Module Level value: 4_level)
539 // DDR / CMOS Input Mode to NA
540 // Open Drain Enable to Disabled
542 // CONFIGURED SETTINGS:
543 // low/high output voltage to CFG(High)
544 // Hyst. Enable to Disabled
545 // Pull / Keep Enable to CFG(Enabled)
546 // Pull / Keep Select to Pull
547 // Pull Up / Down Config. to 100Kohm PU
548 // Drive Strength to CFG(High)
549 // config_pad_settings(NANDF_D11, 0x2004);
550 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D11);
552 // config NANDF_D10 pad for pata instance PATA_DATA[10] port
553 // config_pad_mode(NANDF_D10, 0x1);
554 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D10);
555 // CONSTANT SETTINGS:
556 // test_ts to Disabled
557 // dse test to regular
558 // strength mode to NA (Different from Module Level value: 4_level)
559 // DDR / CMOS Input Mode to NA
560 // Open Drain Enable to Disabled
562 // CONFIGURED SETTINGS:
563 // low/high output voltage to CFG(High)
564 // Hyst. Enable to Disabled
565 // Pull / Keep Enable to CFG(Enabled)
566 // Pull / Keep Select to Pull
567 // Pull Up / Down Config. to 100Kohm PU
568 // Drive Strength to CFG(High)
569 // config_pad_settings(NANDF_D10, 0x2004);
570 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D10);
572 // config NANDF_D9 pad for pata instance PATA_DATA[9] port
573 // config_pad_mode(NANDF_D9, 0x1);
574 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D9);
575 // CONSTANT SETTINGS:
576 // test_ts to Disabled
577 // dse test to regular
578 // strength mode to NA (Different from Module Level value: 4_level)
579 // DDR / CMOS Input Mode to NA
580 // Open Drain Enable to Disabled
582 // CONFIGURED SETTINGS:
583 // low/high output voltage to CFG(High)
584 // Hyst. Enable to Disabled
585 // Pull / Keep Enable to CFG(Enabled)
586 // Pull / Keep Select to Pull
587 // Pull Up / Down Config. to 100Kohm PU
588 // Drive Strength to CFG(High)
589 // config_pad_settings(NANDF_D9, 0x2004);
590 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D9);
592 // config NANDF_D8 pad for pata instance PATA_DATA[8] port
593 // config_pad_mode(NANDF_D8, 0x1);
594 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D8);
595 // CONSTANT SETTINGS:
596 // test_ts to Disabled
597 // dse test to regular
598 // strength mode to NA (Different from Module Level value: 4_level)
599 // DDR / CMOS Input Mode to NA
600 // Open Drain Enable to Disabled
602 // CONFIGURED SETTINGS:
603 // low/high output voltage to CFG(High)
604 // Hyst. Enable to Disabled
605 // Pull / Keep Enable to CFG(Enabled)
606 // Pull / Keep Select to Pull
607 // Pull Up / Down Config. to 100Kohm PU
608 // Drive Strength to CFG(High)
609 // config_pad_settings(NANDF_D8, 0x2004);
610 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D8);
612 // config NANDF_D7 pad for pata instance PATA_DATA[7] port
613 // config_pad_mode(NANDF_D7, 0x1);
614 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D7);
615 // CONSTANT SETTINGS:
616 // test_ts to Disabled
617 // dse test to regular
618 // strength mode to NA (Different from Module Level value: 4_level)
619 // DDR / CMOS Input Mode to NA
620 // Pull Up / Down Config. to 100Kohm PU
621 // Open Drain Enable to Disabled
623 // CONFIGURED SETTINGS:
624 // low/high output voltage to CFG(High)
625 // Hyst. Enable to Disabled
626 // Pull / Keep Enable to CFG(Enabled)
627 // Pull / Keep Select to Pull
628 // Drive Strength to CFG(High)
629 // config_pad_settings(NANDF_D7, 0x2004);
630 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D7);
632 // config NANDF_D6 pad for pata instance PATA_DATA[6] port
633 // config_pad_mode(NANDF_D6, 0x1);
634 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D6);
635 // CONSTANT SETTINGS:
636 // test_ts to Disabled
637 // dse test to regular
638 // strength mode to NA (Different from Module Level value: 4_level)
639 // DDR / CMOS Input Mode to NA
640 // Pull Up / Down Config. to 100Kohm PU
642 // CONFIGURED SETTINGS:
643 // low/high output voltage to CFG(High)
644 // Hyst. Enable to Disabled
645 // Pull / Keep Enable to CFG(Enabled)
646 // Pull / Keep Select to Pull
647 // Open Drain Enable to Disabled
648 // Drive Strength to CFG(High)
649 // config_pad_settings(NANDF_D6, 0x2004);
650 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D6);
652 // config NANDF_D5 pad for pata instance PATA_DATA[5] port
653 // config_pad_mode(NANDF_D5, 0x1);
654 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D5);
655 // CONSTANT SETTINGS:
656 // test_ts to Disabled
657 // dse test to regular
658 // strength mode to NA (Different from Module Level value: 4_level)
659 // DDR / CMOS Input Mode to NA
660 // Pull Up / Down Config. to 100Kohm PU
661 // Open Drain Enable to Disabled
663 // CONFIGURED SETTINGS:
664 // low/high output voltage to CFG(High)
665 // Hyst. Enable to Disabled
666 // Pull / Keep Enable to CFG(Enabled)
667 // Pull / Keep Select to Pull
668 // Drive Strength to CFG(High)
669 // config_pad_settings(NANDF_D5, 0x2004);
670 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D5);
672 // config NANDF_D4 pad for pata instance PATA_DATA[4] port
673 // config_pad_mode(NANDF_D4, 0x1);
674 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D4);
675 // CONSTANT SETTINGS:
676 // test_ts to Disabled
677 // dse test to regular
678 // strength mode to NA (Different from Module Level value: 4_level)
679 // DDR / CMOS Input Mode to NA
680 // Pull Up / Down Config. to 100Kohm PU
681 // Open Drain Enable to Disabled
683 // CONFIGURED SETTINGS:
684 // low/high output voltage to CFG(High)
685 // Hyst. Enable to Disabled
686 // Pull / Keep Enable to CFG(Enabled)
687 // Pull / Keep Select to Pull
688 // Drive Strength to CFG(High)
689 // config_pad_settings(NANDF_D4, 0x2004);
690 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D4);
692 // config NANDF_D3 pad for pata instance PATA_DATA[3] port
693 // config_pad_mode(NANDF_D3, 0x1);
694 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D3);
695 // CONSTANT SETTINGS:
696 // test_ts to Disabled
697 // dse test to regular
698 // strength mode to NA (Different from Module Level value: 4_level)
699 // DDR / CMOS Input Mode to NA
700 // Open Drain Enable to Disabled
702 // CONFIGURED SETTINGS:
703 // low/high output voltage to CFG(High)
704 // Hyst. Enable to Disabled
705 // Pull / Keep Enable to CFG(Enabled)
706 // Pull / Keep Select to Pull
707 // Pull Up / Down Config. to 100Kohm PU
708 // Drive Strength to CFG(High)
709 // config_pad_settings(NANDF_D3, 0x2004);
710 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D3);
712 // config NANDF_D2 pad for pata instance PATA_DATA[2] port
713 // config_pad_mode(NANDF_D2, 0x1);
714 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D2);
715 // CONSTANT SETTINGS:
716 // test_ts to Disabled
717 // dse test to regular
718 // strength mode to NA (Different from Module Level value: 4_level)
719 // DDR / CMOS Input Mode to NA
720 // Open Drain Enable to Disabled
722 // CONFIGURED SETTINGS:
723 // low/high output voltage to CFG(High)
724 // Hyst. Enable to Disabled
725 // Pull / Keep Enable to CFG(Enabled)
726 // Pull / Keep Select to Pull
727 // Pull Up / Down Config. to 100Kohm PU
728 // Drive Strength to CFG(High)
729 // config_pad_settings(NANDF_D2, 0x2004);
730 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D2);
732 // config NANDF_D1 pad for pata instance PATA_DATA[1] port
733 // config_pad_mode(NANDF_D1, 0x1);
734 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D1);
735 // CONSTANT SETTINGS:
736 // test_ts to Disabled
737 // dse test to regular
738 // strength mode to NA (Different from Module Level value: 4_level)
739 // DDR / CMOS Input Mode to NA
740 // Open Drain Enable to Disabled
742 // CONFIGURED SETTINGS:
743 // low/high output voltage to CFG(High)
744 // Hyst. Enable to Disabled
745 // Pull / Keep Enable to CFG(Enabled)
746 // Pull / Keep Select to Pull
747 // Pull Up / Down Config. to 100Kohm PU
748 // Drive Strength to CFG(High)
749 // config_pad_settings(NANDF_D1, 0x2004);
750 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D1);
752 // config NANDF_D0 pad for pata instance PATA_DATA[0] port
753 // config_pad_mode(NANDF_D0, 0x1);
754 writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D0);
755 // CONSTANT SETTINGS:
756 // test_ts to Disabled
757 // dse test to regular
758 // strength mode to NA (Different from Module Level value: 4_level)
759 // DDR / CMOS Input Mode to NA
760 // Open Drain Enable to Disabled
762 // CONFIGURED SETTINGS:
763 // low/high output voltage to CFG(High)
764 // Hyst. Enable to Disabled
765 // Pull / Keep Enable to CFG(Enabled)
766 // Pull / Keep Select to Pull
767 // Pull Up / Down Config. to 100Kohm PU
768 // Drive Strength to CFG(High)
769 // config_pad_settings(NANDF_D0, 0x2004);
770 writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D0);
773 static void mxc_fec_setup(void)
775 volatile unsigned int reg;
777 /* No FEC support for TO 2.0 yet */
778 if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2)
781 writel(0x2, IOMUXC_BASE_ADDR + 0x0390);
782 writel(0x180, IOMUXC_BASE_ADDR + 0x085C);
783 writel(0x1, IOMUXC_BASE_ADDR + 0x09D0);
786 writel(0x2, IOMUXC_BASE_ADDR + 0x0388);
787 writel(0x180, IOMUXC_BASE_ADDR + 0x0854);
788 writel(0x1, IOMUXC_BASE_ADDR + 0x09C4);
791 writel(0x2, IOMUXC_BASE_ADDR + 0x038c);
792 writel(0x180, IOMUXC_BASE_ADDR + 0x0858);
793 writel(0x1, IOMUXC_BASE_ADDR + 0x09C8);
796 writel(0x2, IOMUXC_BASE_ADDR + 0x0384);
797 writel(0x180, IOMUXC_BASE_ADDR + 0x0850);
798 writel(0x1, IOMUXC_BASE_ADDR + 0x9A8);
801 writel(0x2, IOMUXC_BASE_ADDR + 0x0394);
802 writel(0x180, IOMUXC_BASE_ADDR + 0x0860);
803 writel(0x1, IOMUXC_BASE_ADDR + 0x09B4);
806 writel(0x2, IOMUXC_BASE_ADDR + 0x0398);
807 writel(0x5, IOMUXC_BASE_ADDR + 0x864);
810 writel(0x2, IOMUXC_BASE_ADDR + 0x0380);
811 writel(0x5, IOMUXC_BASE_ADDR + 0x084C);
814 writel(0x2, IOMUXC_BASE_ADDR + 0x034C);
815 writel(0x5, IOMUXC_BASE_ADDR + 0x0818);
818 writel(0x2, IOMUXC_BASE_ADDR + 0x0350);
819 writel(0x1CD, IOMUXC_BASE_ADDR + 0x081C);
820 writel(0x1, IOMUXC_BASE_ADDR + 0x09B0);
823 writel(0x2, IOMUXC_BASE_ADDR + 0x0344);
824 writel(0x5, IOMUXC_BASE_ADDR + 0x0810);
827 writel(0x2, IOMUXC_BASE_ADDR + 0x0360);
828 writel(0x180, IOMUXC_BASE_ADDR + 0x082C);
829 writel(0x1, IOMUXC_BASE_ADDR + 0x09CC);
832 writel(0x2, IOMUXC_BASE_ADDR + 0x0348);
833 writel(0x180, IOMUXC_BASE_ADDR + 0x0814);
834 writel(0x1, IOMUXC_BASE_ADDR + 0x09AC);
837 writel(0x2, IOMUXC_BASE_ADDR + 0x0354);
838 writel(0x180, IOMUXC_BASE_ADDR + 0x0820);
839 writel(0x1, IOMUXC_BASE_ADDR + 0x09B8);
842 writel(0x2, IOMUXC_BASE_ADDR + 0x0374);
843 writel(0x5, IOMUXC_BASE_ADDR + 0x0840);
846 writel(0x2, IOMUXC_BASE_ADDR + 0x0358);
847 writel(0x180, IOMUXC_BASE_ADDR + 0x0824);
848 writel(0x1, IOMUXC_BASE_ADDR + 0x09BC);
851 writel(0x2, IOMUXC_BASE_ADDR + 0x0378);
852 writel(0x5, IOMUXC_BASE_ADDR + 0x0844);
855 writel(0x2, IOMUXC_BASE_ADDR + 0x035C);
856 writel(0x180, IOMUXC_BASE_ADDR + 0x0828);
857 writel(0x1, IOMUXC_BASE_ADDR + 0x09C0);
860 writel(0x2, IOMUXC_BASE_ADDR + 0x037C);
861 writel(0x5, IOMUXC_BASE_ADDR + 0x0848);
863 reg = readl(GPIO3_BASE_ADDR + 0x0);
864 reg &= ~0x40; // Lower reset line
865 writel(reg, GPIO3_BASE_ADDR + 0x0);
867 reg = readl(GPIO3_BASE_ADDR + 0x4);
868 reg |= 0x40; // configure GPIO lines as output
869 writel(reg, GPIO3_BASE_ADDR + 0x4);
871 /* Reset the ethernet controller over GPIO */
872 writel(0x4, IOMUXC_BASE_ADDR + 0x02CC);
873 writel(0xC5, IOMUXC_BASE_ADDR + 0x078C);
877 reg = readl(GPIO3_BASE_ADDR + 0x0);
879 writel(reg, GPIO3_BASE_ADDR + 0x0);
882 static void mxc_nfc_iomux_setup(void)
884 if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
885 writel(0x0, IOMUXC_BASE_ADDR + 0x108);
886 writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
887 writel(0x0, IOMUXC_BASE_ADDR + 0x110);
888 writel(0x0, IOMUXC_BASE_ADDR + 0x114);
889 writel(0x0, IOMUXC_BASE_ADDR + 0x118);
890 writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
891 writel(0x0, IOMUXC_BASE_ADDR + 0x120);
892 writel(0x0, IOMUXC_BASE_ADDR + 0x124);
893 writel(0x0, IOMUXC_BASE_ADDR + 0x128);
894 writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
895 writel(0x0, IOMUXC_BASE_ADDR + 0x130);
896 writel(0x0, IOMUXC_BASE_ADDR + 0x134);
897 writel(0x0, IOMUXC_BASE_ADDR + 0x138);
898 writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
899 writel(0x0, IOMUXC_BASE_ADDR + 0x140);
900 writel(0x0, IOMUXC_BASE_ADDR + 0x144);
901 writel(0x0, IOMUXC_BASE_ADDR + 0x148);
902 writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
903 writel(0x0, IOMUXC_BASE_ADDR + 0x150);
904 writel(0x0, IOMUXC_BASE_ADDR + 0x154);
905 writel(0x0, IOMUXC_BASE_ADDR + 0x158);
906 writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
907 writel(0x0, IOMUXC_BASE_ADDR + 0x160);
908 writel(0x0, IOMUXC_BASE_ADDR + 0x164);
909 writel(0x0, IOMUXC_BASE_ADDR + 0x168);
910 writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
911 writel(0x0, IOMUXC_BASE_ADDR + 0x170);
912 writel(0x0, IOMUXC_BASE_ADDR + 0x174);
913 writel(0x0, IOMUXC_BASE_ADDR + 0x178);
914 writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
915 writel(0x0, IOMUXC_BASE_ADDR + 0x180);
916 writel(0x0, IOMUXC_BASE_ADDR + 0x184);
917 writel(0x0, IOMUXC_BASE_ADDR + 0x188);
918 writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
919 writel(0x0, IOMUXC_BASE_ADDR + 0x190);
921 writel(0x0, IOMUXC_BASE_ADDR + 0x108);
922 writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
923 writel(0x0, IOMUXC_BASE_ADDR + 0x110);
924 writel(0x0, IOMUXC_BASE_ADDR + 0x114);
925 writel(0x0, IOMUXC_BASE_ADDR + 0x118);
926 writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
927 writel(0x0, IOMUXC_BASE_ADDR + 0x120);
928 writel(0x0, IOMUXC_BASE_ADDR + 0x124);
929 writel(0x0, IOMUXC_BASE_ADDR + 0x128);
930 writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
931 writel(0x0, IOMUXC_BASE_ADDR + 0x130);
932 writel(0x0, IOMUXC_BASE_ADDR + 0x134);
933 writel(0x0, IOMUXC_BASE_ADDR + 0x138);
934 writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
935 writel(0x0, IOMUXC_BASE_ADDR + 0x140);
936 writel(0x0, IOMUXC_BASE_ADDR + 0x144);
937 writel(0x0, IOMUXC_BASE_ADDR + 0x148);
938 writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
939 writel(0x0, IOMUXC_BASE_ADDR + 0x150);
940 writel(0x0, IOMUXC_BASE_ADDR + 0x154);
941 writel(0x0, IOMUXC_BASE_ADDR + 0x158);
942 writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
943 writel(0x0, IOMUXC_BASE_ADDR + 0x160);
944 writel(0x0, IOMUXC_BASE_ADDR + 0x164);
945 writel(0x0, IOMUXC_BASE_ADDR + 0x168);
946 writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
947 writel(0x0, IOMUXC_BASE_ADDR + 0x170);
948 writel(0x0, IOMUXC_BASE_ADDR + 0x174);
949 writel(0x0, IOMUXC_BASE_ADDR + 0x178);
950 writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
951 writel(0x0, IOMUXC_BASE_ADDR + 0x180);
952 writel(0x0, IOMUXC_BASE_ADDR + 0x184);
953 writel(0x0, IOMUXC_BASE_ADDR + 0x188);
954 writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
955 writel(0x0, IOMUXC_BASE_ADDR + 0x190);
956 writel(0x0, IOMUXC_BASE_ADDR + 0x194);
957 writel(0x0, IOMUXC_BASE_ADDR + 0x198);
958 writel(0x0, IOMUXC_BASE_ADDR + 0x19C);
963 // Platform specific initialization
966 void plf_hardware_init(void)
968 unsigned long sw_rest_reg, weim_base;
970 unsigned char buf[4];
971 struct mxc_i2c_request rq;
973 /* Atlas Workaround needed only for TO 1.0 and 1.1 boards */
974 if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) != 0x2) {
975 if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
983 /* Make sure we implement this workaround only for boards with Atlas-Lite to turn off the charger */
984 if ((buf[1] == 0x41) && (buf[2] == 0xc8 || buf[2] == 0xc9)) {
999 writel(0, IOMUXC_BASE_ADDR + 0xF4);
1000 weim_base = WEIM_BASE_ADDR + 0x78;
1001 writel(0x00410089, weim_base + CSGCR1);
1002 writel(0x00000002, weim_base + CSGCR2);
1003 // RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0
1004 writel(0x32260000, weim_base + CSRCR1);
1006 writel(0x00000000, weim_base + CSRCR2);
1007 // WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0, WCSN=0
1008 writel(0x72080F00, weim_base + CSWCR1);
1009 cpld_base_addr = CS5_BASE_ADDR;
1011 /* Reset interrupt status reg */
1012 writew(0x1F, cpld_base_addr + PBC_INT_REST);
1013 writew(0x00, cpld_base_addr + PBC_INT_REST);
1014 writew(0xFFFF, cpld_base_addr + PBC_INT_MASK);
1016 /* Reset the XUART and Ethernet controllers */
1017 sw_rest_reg = readw(cpld_base_addr + PBC_SW_RESET);
1019 writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
1020 sw_rest_reg &= ~0x9;
1021 writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
1023 if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
1026 writel(0x0, IOMUXC_BASE_ADDR + 0x228);
1027 writel(0x1C5, IOMUXC_BASE_ADDR + 0x618);
1029 writel(0x0, IOMUXC_BASE_ADDR + 0x22c);
1030 writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c);
1032 writel(0x0, IOMUXC_BASE_ADDR + 0x230);
1033 writel(0x1C4, IOMUXC_BASE_ADDR + 0x620);
1035 writel(0x0, IOMUXC_BASE_ADDR + 0x234);
1036 writel(0x1C4, IOMUXC_BASE_ADDR + 0x624);
1037 // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
1038 writel(0x00000004, 0x73fa83E8);
1039 writel(0x00000004, 0x73fa83Ec);
1043 writel(0x0, IOMUXC_BASE_ADDR + 0x234);
1044 writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E4);
1046 writel(0x0, IOMUXC_BASE_ADDR + 0x238);
1047 writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E8);
1049 writel(0x0, IOMUXC_BASE_ADDR + 0x23C);
1050 writel(0x1C4, IOMUXC_BASE_ADDR + 0x6EC);
1052 writel(0x0, IOMUXC_BASE_ADDR + 0x240);
1053 writel(0x1C4, IOMUXC_BASE_ADDR + 0x6F0);
1054 // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
1055 writel(0x00000004, 0x73fa83F4);
1056 writel(0x00000004, 0x73fa83F0);
1059 // enable ARM clock div by 8
1060 writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
1061 #ifdef MXCFLASH_SELECT_NAND
1062 nfc_iomux_setup = (nfc_iomuxsetup_func_t*)mxc_nfc_iomux_setup;
1067 void mxc_mmc_init(unsigned int base_address)
1069 switch(base_address) {
1070 case MMC_SDHC1_BASE_ADDR:
1071 if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
1072 /* SD1 CMD, SION bit */
1073 writel(0x10, IOMUXC_BASE_ADDR + 0x394);
1074 /* Configure SW PAD */
1076 writel(0x20d4, IOMUXC_BASE_ADDR + 0x79C);
1078 writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A0);
1080 writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A4);
1082 writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A8);
1084 writel(0x20d4, IOMUXC_BASE_ADDR + 0x7AC);
1086 writel(0x20d4, IOMUXC_BASE_ADDR + 0x7B0);
1088 /* SD1 CMD, SION bit */
1089 writel(0x10, IOMUXC_BASE_ADDR + 0x39c);
1090 /* SD1 CD, as gpio1_0 */
1091 writel(0x01, IOMUXC_BASE_ADDR + 0x3b4);
1092 /* Configure SW PAD */
1094 writel(0x20d4, IOMUXC_BASE_ADDR + 0x868);
1096 writel(0x20d4, IOMUXC_BASE_ADDR + 0x86c);
1098 writel(0x20d4, IOMUXC_BASE_ADDR + 0x870);
1100 writel(0x20d4, IOMUXC_BASE_ADDR + 0x874);
1102 writel(0x20d4, IOMUXC_BASE_ADDR + 0x878);
1104 writel(0x20d4, IOMUXC_BASE_ADDR + 0x87c);
1105 /* SD1 CD as gpio1_0 */
1106 writel(0x1e2, IOMUXC_BASE_ADDR + 0x880);
1114 void increase_core_voltage(bool i)
1116 unsigned char buf[4];
1117 struct mxc_i2c_request rq;
1126 i2c_xfer(1, &rq, 1);
1129 buf[2] = buf[2] & (~0x1F) | 0x17;
1131 buf[2] = buf[2] & (~0x1F) | 0x12;
1133 i2c_xfer(1, &rq, 0);
1136 #include CYGHWR_MEMORY_LAYOUT_H
1138 typedef void code_fun(void);
1140 void board_program_new_stack(void *func)
1142 register CYG_ADDRESS stack_ptr asm("sp");
1143 register CYG_ADDRESS old_stack asm("r4");
1144 register code_fun *new_func asm("r0");
1145 old_stack = stack_ptr;
1146 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
1147 new_func = (code_fun*)func;
1149 stack_ptr = old_stack;