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34 # ====================================================================
35 ######DESCRIPTIONBEGIN####
38 # Original data: gthomas
42 #####DESCRIPTIONEND####
44 # ====================================================================
45 cdl_package CYGPKG_HAL_ARM_MX51 {
46 display "Freescale SoC architecture"
50 define_header hal_arm_soc.h
52 This HAL variant package provides generic
53 support for the Freescale SoC. It is also
54 necessary to select a specific target platform HAL
57 implements CYGINT_HAL_ARM_ARCH_ARM9
58 implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
60 # Let the architectural HAL see this variant's interrupts file -
61 # the SoC has no variation between targets here.
63 puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
64 puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
66 puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
69 compile soc_diag.c soc_misc.c
70 compile -library=libextras.a cmds.c
72 cdl_option CYGHWR_MX51_TO2 {
73 display "MX51 Tapeout 2.0 support"
76 When this option is enabled, it indicates support for
79 puts $::cdl_system_header "#define IMX51_TO_2"
83 cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
84 display "Processor clock rate"
85 active_if { CYG_HAL_STARTUP == "ROM" }
87 legal_values 150000 200000
88 default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
89 CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000}
91 The processor can run at various frequencies.
92 These values are expressed in KHz. Note that there are
93 several steppings of the rated to run at different
94 maximum frequencies. Check the specs to make sure that your
95 particular processor can run at the rate you select here."
98 # Real-time clock/counter specifics
99 cdl_component CYGNUM_HAL_RTC_CONSTANTS {
100 display "Real-time clock constants"
104 cdl_option CYGNUM_HAL_RTC_NUMERATOR {
105 display "Real-time clock numerator"
107 calculated 1000000000
109 cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
110 display "Real-time clock denominator"
114 This option selects the heartbeat rate for the real-time clock.
115 The rate is specified in ticks per second. Change this value
116 with caution - too high and your system will become saturated
117 just handling clock interrupts, too low and some operations
118 such as thread scheduling may become sluggish."
120 cdl_option CYGNUM_HAL_RTC_PERIOD {
121 display "Real-time clock period"
123 calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) ;# Clock for OS Timer is 3.6864MHz
127 # Control over hardware layout.
128 cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
129 display "UART1 available as diagnostic/debug channel"
131 The chip has multiple serial channels which may be
132 used for different things on different platforms. This
133 interface allows a platform to indicate that the specified
134 serial port can be used as a diagnostic and/or debug channel."
137 cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
138 display "UART2 available as diagnostic/debug channel"
140 The chip has multiple serial channels which may be
141 used for different things on different platforms. This
142 interface allows a platform to indicate that the specified
143 serial port can be used as a diagnostic and/or debug channel."
146 cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
147 display "UART3 available as diagnostic/debug channel"
149 The chip has multiple serial channels which may be
150 used for different things on different platforms. This
151 interface allows a platform to indicate that the specified
152 serial port can be used as a diagnostic and/or debug channel."
155 cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
156 display "UART4 available as diagnostic/debug channel"
158 The chip has multiple serial channels which may be
159 used for different things on different platforms. This
160 interface allows a platform to indicate that the specified
161 serial port can be used as a diagnostic and/or debug channel."
164 cdl_interface CYGHWR_HAL_ARM_SOC_UART5 {
165 display "UART5 available as diagnostic/debug channel"
167 The chip has multiple serial channels which may be
168 used for different things on different platforms. This
169 interface allows a platform to indicate that the specified
170 serial port can be used as a diagnostic and/or debug channel."
173 cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
174 display "FEC ethernet driver required"
177 implements CYGINT_DEVS_ETH_FEC_REQUIRED