1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
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30 // or inline functions from this file, or you compile this file and link it
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 #define CYGHWR_HAL_ROM_VADDR 0x0
61 #undef CLOCK_SETUP_ALIGNED
63 // This macro represents the initial startup code for the platform
64 .macro _platform_setup1
65 FSL_BOARD_SETUP_START:
68 * - invalidate I/D cache/TLB and drain write buffer;
69 * - invalidate L2 cache
71 * - branch predictions
73 #ifdef TURN_OFF_IMPRECISE_ABORT
79 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
80 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
81 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
83 /* Also setup the Peripheral Port Remap register inside the core */
84 ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
85 mcr p15, 0, r0, c15, c2, 4
87 /*** L2 Cache setup/invalidation/disable ***/
88 /* Disable L2 cache first */
89 mov r0, #L2CC_BASE_ADDR
90 ldr r2, [r0, #L2_CACHE_CTL_REG]
92 str r2, [r0, #L2_CACHE_CTL_REG]
95 * - 128k size(16k way)
96 * - 8-way associativity
97 * - 0 ws TAG/VALID/DIRTY
100 ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
101 and r1, r1, #0xFE000000
102 ldr r2, L2CACHE_PARAM
104 str r1, [r0, #L2_CACHE_AUX_CTL_REG]
108 str r1, [r0, #L2_CACHE_INV_WAY_REG]
110 /* Poll Invalidate By Way register */
111 ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
114 /*** End of L2 operations ***/
116 mov r0, #SDRAM_NON_FLASH_BOOT
117 ldr r1, AVIC_VECTOR0_ADDR_W
118 str r0, [r1] // for checking boot source from nand, nor or sdram
120 * End of ARM1136 init
133 // If SDRAM has been setup, bypass clock/WEIM setup
134 cmp pc, #SDRAM_BASE_ADDR
136 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
137 blo HWInitialise_skip_SDRAM_setup
139 mov r0, #NOR_FLASH_BOOT
140 ldr r1, AVIC_VECTOR0_ADDR_W
143 // Disable the SDCLK by clearing SDE (bit 31) in ESDCTL0 and ESDCTL1
144 // (as the DDR chip needs a stable clock after CKE is high)
145 ldr r0, ESDCTL_BASE_W
146 ldr r1, SDRAM_0x02216080
147 str r1, [r0, #ESDCTL_ESDCTL0]
148 str r1, [r0, #ESDCTL_ESDCTL1]
156 HWInitialise_skip_SDRAM_setup:
159 add r2, r0, #0x800 // 2K window
161 blo Normal_Boot_Continue
163 bhi Normal_Boot_Continue
165 /* Copy image from flash to SDRAM first */
166 ldr r1, MXC_REDBOOT_ROM_START
168 1: ldmia r0!, {r3-r10}
174 and r0, pc, r1 /* offset of pc */
175 ldr r1, MXC_REDBOOT_ROM_START
183 mov r0, #NAND_FLASH_BOOT
184 ldr r1, AVIC_VECTOR0_ADDR_W
187 ldr r1, AVIC_VECTOR1_ADDR_W
190 mov r0, #NFC_BASE; //r0: nfc base. Reloaded after each page copying
191 mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
192 add r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
193 add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
194 ldr r14, MXC_REDBOOT_ROM_START
195 add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
196 add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
198 //unlock internal buffer
203 // writew(FLASH_Read_Mode1, NAND_FLASH_CMD_REG);
205 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
206 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
207 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
210 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
212 do_addr_input //1st addr cycle
214 do_addr_input //2nd addr cycle
216 do_addr_input //3rd addr cycle
218 do_addr_input //4th addr cycle
220 // NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
221 // writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
222 // NAND_FLASH_CONFIG1_REG);
223 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
224 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
226 // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
228 strh r3, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
229 // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
230 mov r3, #FDO_PAGE_SPARE_VAL
231 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
235 // check for bad block
236 mov r3, r1, lsl #(32-5-9)
237 cmp r3, #(512 << (32-5-9))
239 add r4, r0, #0x800 //r3 -> spare area buf 0
244 // really sucks. Bad block!!!!
247 // even suckier since we already read the first page!
248 sub r14, r14, #512 //rewind 1 page for the sdram pointer
249 sub r1, r1, #512 //rewind 1 page for the flash pointer
251 add r1, r1, #(32*512)
255 1: ldmia r0!, {r3-r10}
260 bge NAND_Copy_Main_done
267 Normal_Boot_Continue:
269 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
270 /* Copy image from flash to SDRAM first */
273 ldr r1, MXC_REDBOOT_ROM_START
275 beq HWInitialise_skip_SDRAM_copy
277 add r2, r0, #REDBOOT_IMAGE_SIZE
279 1: ldmia r0!, {r3-r10}
285 and r0, pc, r1 /* offset of pc */
286 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
292 #endif /* CYG_HAL_STARTUP_ROMRAM */
294 HWInitialise_skip_SDRAM_copy:
303 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
307 // Set up a stack [for calling C code]
308 ldr r1, =__startup_stack
309 ldr r2, =RAM_BANK0_BASE
317 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
318 orr r1, r1, #7 // enable MMU bit
319 orr r1, r1, #0x800 // enable z bit
320 mcr MMU_CP, 0, r1, MMU_Control, c0
321 mov pc,r2 /* Change address spaces */
327 // Save shadow copy of BCR, also hardware configuration
331 str r9, [r1] // Saved far above...
333 .endm // _platform_setup1
335 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
336 #define PLATFORM_SETUP1
339 /* Allow all 3 masters to have access to these shared peripherals */
341 ldr r0, SPBA_CTRL_BASE_ADDR_W
343 ldr r1, =0x7 /* allow all 3 masters access */
344 ldr r2, SPBA_LOCK_VAL
354 .endm /* init_spba */
356 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
359 * Set all MPROTx to be non-bufferable, trusted for R/W,
360 * not forced to user-mode.
362 ldr r0, AIPS1_CTRL_BASE_ADDR_W
363 ldr r1, AIPS1_PARAM_W
366 ldr r0, AIPS2_CTRL_BASE_ADDR_W
371 * Clear the on and off peripheral modules Supervisor Protect bit
372 * for SDMA to access them. Did not change the AIPS control registers
373 * (offset 0x20) access type
375 ldr r0, AIPS1_CTRL_BASE_ADDR_W
382 and r1, r1, #0x00FFFFFF
385 ldr r0, AIPS2_CTRL_BASE_ADDR_W
392 and r1, r1, #0x00FFFFFF
394 .endm /* init_aips */
396 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
398 ldr r0, MAX_BASE_ADDR_W
399 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
401 str r1, [r0, #0x000] /* for S0 */
402 str r1, [r0, #0x100] /* for S1 */
403 str r1, [r0, #0x200] /* for S2 */
404 str r1, [r0, #0x300] /* for S3 */
405 str r1, [r0, #0x400] /* for S4 */
406 /* SGPCR - always park on last master */
408 str r1, [r0, #0x010] /* for S0 */
409 str r1, [r0, #0x110] /* for S1 */
410 str r1, [r0, #0x210] /* for S2 */
411 str r1, [r0, #0x310] /* for S3 */
412 str r1, [r0, #0x410] /* for S4 */
413 /* MGPCR - restore default values */
415 str r1, [r0, #0x800] /* for M0 */
416 str r1, [r0, #0x900] /* for M1 */
417 str r1, [r0, #0xA00] /* for M2 */
418 str r1, [r0, #0xB00] /* for M3 */
419 str r1, [r0, #0xC00] /* for M4 */
420 str r1, [r0, #0xD00] /* for M5 */
425 #ifdef CLOCK_SETUP_ALIGNED
430 ldr r0, CRM_MCU_BASE_ADDR_W
431 // enable MPLL, UPLL, TurboPLL
432 ldr r1, CRM_MCR_0x18FF2952
433 str r1, [r0, #CLKCTL_MCR]
436 ldr r1, [r0, #CLKCTL_MCR]
440 #if 1 // for 133MHz HCLK
441 ldr r1, TPCTL_PARAM_532_W
442 str r1, [r0, #CLKCTL_TPCTL]
443 ldr r1, PDR0_399_133_66_W
445 ldr r1, TPCTL_PARAM_500_W
446 str r1, [r0, #CLKCTL_TPCTL]
447 ldr r1, PDR0_399_100_50_W
450 // add some delay here
455 #ifdef CLOCK_SETUP_ALIGNED
460 str r1, [r0, #CLKCTL_PDR0]
461 ldr r1, MPCTL_PARAM_399_W
462 str r1, [r0, #CLKCTL_MPCTL]
464 /* Set to default values */
465 ldr r1, PDR1_0x2910AC56_W
466 str r1, [r0, #CLKCTL_PDR1]
467 /* Set UPLL=288MHz */
468 ldr r1, UPCTL_PARAM_288_W
469 str r1, [r0, #CLKCTL_UPCTL]
472 * J10 (CPU card) - CKO1=MCU_PLL div by 8
473 * J9 (CPU card) - CKO2=IPG_CLK_ARM div by 8
475 ldr r1, CRM_COSR_0x00036C58
476 str r1, [r0, #CLKCTL_COSR]
477 .endm /* init_clock */
481 /* Configure M3IF registers */
484 * M3IF Control Register (M3IFCTL)
485 * MRRP[0] = TMAX not on priority list (0 << 0) = 0x00000000
486 * MRRP[1] = SMIF not on priority list (0 << 0) = 0x00000000
487 * MRRP[2] = MAX0 not on priority list (0 << 0) = 0x00000000
488 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
489 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
490 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
491 * MRRP[6] = IPU on priority list (1 << 6) = 0x00000040
492 * MRRP[7] = SMIF-L2CC not on priority list (0 << 0) = 0x00000000
497 str r0, [r1] /* M3IF control reg */
498 .endm /* init_m3if */
500 /* CS0 sync mode setup */
502 // setup the sync mode in the flash itself first
503 mov r0, #CS0_BASE_ADDR
504 add r0, r0, #0x00004300
509 // setup the sync mode in the WEIM
510 ldr r0, WEIM_BASE_ADDR_W
511 ldr r1, CS0_CSCRU_0x23D29000
513 ldr r1, CS0_CSCRL_0x60000D01
517 .endm /* init_cs0_sync */
519 /* CS0 async mode setup */
520 .macro init_cs0_async
521 // setup the async mode in the flash itself first
522 mov r0, #CS0_BASE_ADDR
523 add r0, r0, #0x00017000
524 add r0, r0, #0x00000700
529 /* CS0 setup: Configuring the CS0 in Asynchronous mode */
530 ldr r0, WEIM_BASE_ADDR_W /* 0xB8002000 */
531 ldr r1, CS0_CSCRU_0x23C29000 /* no sync/burst */
532 str r1, [r0, #CSCRU] /* +0x00 */
533 ldr r1, CS0_CSCRL_0x60000D01 /* 16-bit port, CS enabled */
534 str r1, [r0, #CSCRL] /* +0x04 */
535 mov r1, #0x00000080 /* decrease Write Wait State enabled */
536 str r1, [r0, #CSCRA] /* +0x08 */
537 .endm /* init_cs0_async */
544 ldr r0, =WEIM_CTRL_CS2
554 .macro init_ddr_sdram
555 ldr r0, ESDCTL_BASE_W
556 ldr r2, IOMUXC_BASE_ADDR_W
557 mov r12, #SDRAM_BASE_ADDR
559 // 3. Enable the SDCLK by setting SDE (bit 31) in ESDCTL1
560 // reg32_write(ESDCTL1, 0x82216080);
561 ldr r1, SDRAM_0x02216080
562 add r1, r1, #0x80000000
563 str r1, [r0, #ESDCTL_ESDCTL1]
564 // 4. Put the CSD0 controller in Manual Self Refresh, with SREFR=0
565 // and PWDT=2 or 3. This step is needed to be able to enter properly
566 // the Low Power modes
567 // reg32_write(ESDCTL0, (0xc2216080 & 0xffff13ff) + (3<<10));
568 ldr r1, SDRAM_0x02210C80
569 str r1, [r0, #ESDCTL_ESDCTL0]
570 // 5. Wait for the SDRAMRDY bit (bit 31 in ESDMISC) to be set. This bit
571 // indicates that the SDRAM is ready for use.
573 ldr r1, [r0, #ESDCTL_ESDMISC]
574 ands r1, r1, #0x80000000
576 // 6. Reset the ESDCTL and the ESDCTL delay lines:
577 // reg32_write(ESDMISC, 0x000000f)
579 str r1, [r0, #ESDCTL_ESDMISC]
580 // 7. Set the proper delay lines correction:
581 // reg32_write(ESDCDLY1, 0x00280000);
582 // reg32_write(ESDCDLY2, 0x00280000);
583 // reg32_write(ESDCDLY5, 0x003e0000);
584 // For Read, only ESDCDLY1 and ESDCDLY2 have to be initialized, as 16
585 // bit memory is used.
587 str r1, [r0, #ESDCTL_ESDCDLY1]
588 str r1, [r0, #ESDCTL_ESDCDLY2]
590 str r1, [r0, #ESDCTL_ESDCDLY5]
591 // 8. Configure the ESDCTL timing parameters (see Table 4 for details):
592 // reg32_write(ESDCFG1, 0x00795729);
593 ldr r1, SDRAM_0x00795729
594 str r1, [r0, #ESDCTL_ESDCFG1]
595 // 9. Remove ESDRAMC reset (this step is not mandatory, as the RST bit in
596 // ESDMISC is auto-clearing)
597 // reg32_write(ESDMISC, 0x0000000d);
599 str r1, [r0, #ESDCTL_ESDMISC]
600 // 10. Set the pads drive strengths / DDR mode (MCU accesses):
601 // reg32_write(0x500003d0, 0x00000007);//sw_pad_ctl_sdqs0="111"
602 // reg32_write(0x500003c4, 0x00001800);//sw_pad_ctl_oe_b="110"
603 // reg32_write(0x500003C8, 0x00700000);//sw_pad_ctl_dqm0="111"
604 // reg32_write(0x500003F8, 0x00700000);//sw_pad_ctl_sd0="111"
605 // reg32_write(0x5000041C, 0x00700000);//sw_pad_ctl_a0_ma0='111'
618 // 11. Wait for 200us (as the DDR clock must be stable for at least
619 // 200us and the delay line measurement needs at least 16us after
620 // a reset before being operational).
626 // 12. Send a Precharge command to all banks, using a Byte access with A10 high.
627 // reg32_write(ESDCTL1, 0x92216080);
628 // reg8_write(0x90000400, 0x00);
629 ldr r1, SDRAM_0x92216080
630 str r1, [r0, #ESDCTL_ESDCTL1]
632 strb r1, [r12, #0x400]
634 // 13. Send (at least) 2 AutoRefresh commands. They must be separated by at
635 // least tRFC = 75ns (10 tck at 133 MHz)
636 // reg32_write(ESDCTL1, 0xA2216080);
637 // reg16_write(0x90000000, 0x0000);
639 // reg16_write(0x90000000, 0x0000);
640 ldr r1, SDRAM_0xA2216080
641 str r1, [r0, #ESDCTL_ESDCTL1]
652 // 14. Place the SDCTL in Load Mode Register Command mode
653 // reg32_write(ESDCTL1, 0xB2216080);
654 ldr r1, SDRAM_0xB2216080
655 str r1, [r0, #ESDCTL_ESDCTL1]
656 // 15. Set the DDR Mode Register. Set the Burst Size to 8, the Burst Mode
657 // to Sequential, the CAS latency to 3. Byte Access is required.
658 // reg8_write(0x90000033, 0x00);
660 strb r1, [r12, #0x33]
661 // 16. Set the DDR Extended Mode Register. The DDR drive strength should
662 // be set to Full Drive. The access is done in Bank 2. A Byte Access
664 // (There should be at least tMRD = 15ns between the access to MR
665 // and EMR, but this is taken care by SDCTL).
666 // reg8_write(0x92000000, 0x00);
667 add r11, r12, #0x02000000
669 // 17. Put the DDR controller in Normal operating mode
670 // reg32_write(ESDCTL1, 0x82216080);
671 ldr r3, SDRAM_0x82216080 /* 16 bit memory */
672 str r3, [r0, #ESDCTL_ESDCTL1]
673 // 18. Perform a 16-bit Read
674 // reg32_read(0x90000000);
678 .macro do_wait_op_done
680 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
681 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
684 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
685 .endm // do_wait_op_done
689 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
690 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
691 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
693 .endm // do_addr_input
695 /* To support 133MHz SDR */
696 .macro init_drive_strength
697 // No need to change the default drive strength for DDR
698 .endm /* init_drive_strength */
702 * Deal with DSP reset
708 beq skip_dsp_switch_le
709 bic r1, r1, #(1 << 5)
713 /* Put DSP in reset */
717 /* Hold for some time */
723 /* Put DSP out of reset */
727 #define PLATFORM_VECTORS _platform_vectors
728 .macro _platform_vectors
729 .globl _board_BCR, _board_CFG
730 _board_BCR: .long 0 // Board Control register shadow
731 _board_CFG: .long 0 // Board Configuration (read at RESET)
734 #define PLATFORM_PREAMBLE _switch_to_le
737 .word 0xEE110F10 // mrc 15, 0, r0, c1, c0, 0
738 .word 0xE3C00080 // bic r0, r0, #0x80
739 .word 0xEE010F10 // mcr 15, 0, r0, c1, c0, 0
741 .word 0x0F10EE11 // mrc 15, 0, r0, c1, c0, 0
742 .word 0x0080E3C0 // bic r0, r0, #0x80
743 .word 0x0F10EE01 // mcr 15, 0, r0, c1, c0, 0
754 #if 0 /// good for SDRAM since 32bit
755 .word 0xEE110F10 // mrc 15, 0, r0, c1, c0, 0
756 .word 0xE3C00080 // bic r0, r0, #0x80
757 .word 0xEE010F10 // mcr 15, 0, r0, c1, c0, 0
760 ARM_PPMRR: .word 0x40000015
761 L2CACHE_PARAM: .word 0x00030024
762 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
763 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
764 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
765 AIPS1_PARAM_W: .word 0x77777777
766 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
767 MAX_PARAM1: .word 0x00302154
768 RVAL_WVAL_W: .word 0x515
769 CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
770 CRM_MCR_0x18FF2902: .word 0x18FF2902
771 CRM_MCR_0x18FF2952: .word 0x18FF2952
772 CRM_COSR_0x00036C58: .word 0x00036C58
773 PDR0_399_100_50_W: .word PDR0_399_100_50
774 PDR0_399_133_66_W: .word PDR0_399_133_66
775 PDR0_399_66_66_W: .word PDR0_399_66_66
776 PDR1_0x2910AC56_W: .word 0x2910AC56
777 MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
778 UPCTL_PARAM_288_W: .word UPCTL_PARAM_288
779 TPCTL_PARAM_500_W: .word TPCTL_PARAM_500
780 TPCTL_PARAM_532_W: .word TPCTL_PARAM_532
781 SPBA_CTRL_BASE_ADDR_W: .word SPBA_CTRL_BASE_ADDR
782 SPBA_LOCK_VAL: .word 0xC0010007
783 ESDCTL_BASE_W: .word ESDCTL_BASE
784 M3IF_BASE_W: .word M3IF_BASE
785 SDRAM_0x02216080: .word 0x02216080
786 SDRAM_0x82216080: .word 0x82216080
787 SDRAM_0x92216080: .word 0x92216080
788 SDRAM_0xA2216080: .word 0xA2216080
789 SDRAM_0xB2216080: .word 0xB2216080
790 SDRAM_0x00795729: .word 0x00795729
791 SDRAM_0x02210C80: .word 0x02210C80
792 WEIM_BASE_ADDR_W: .word WEIM_BASE_ADDR
793 CS0_CSCRU_0x23C29000: .word 0x23C29000
794 CS0_CSCRL_0x60000D01: .word 0x60000D01
795 CS0_CSCRU_0x23D29000: .word 0x23D29000
796 DS_0x12449D24: .word 0x12449D24
797 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
798 CRM_MCU_BASE_ADDR_W: .word CRM_MCU_BASE_ADDR
799 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
800 CONST_0x0FFF: .word 0x0FFF
801 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
802 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
804 /*---------------------------------------------------------------------------*/
805 /* end of hal_platform_setup.h */
806 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */