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34 # ====================================================================
35 ######DESCRIPTIONBEGIN####
38 # Original data: gthomas
42 #####DESCRIPTIONEND####
44 # ====================================================================
45 cdl_package CYGPKG_HAL_ARM_MXC91321 {
46 display "Freescale SoC architecture"
50 define_header hal_arm_soc.h
52 This HAL variant package provides generic
53 support for the Freescale SoC. It is also
54 necessary to select a specific target platform HAL
57 implements CYGINT_HAL_ARM_ARCH_ARM9
58 implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
60 # Let the architectural HAL see this variant's interrupts file -
61 # the SoC has no variation between targets here.
63 puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
64 puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
66 puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
69 compile soc_diag.c soc_misc.c
70 compile -library=libextras.a cmds.c
72 cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
73 display "Processor clock rate"
74 active_if { CYG_HAL_STARTUP == "ROM" }
76 legal_values 150000 200000
77 default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
78 CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000}
80 The processor can run at various frequencies.
81 These values are expressed in KHz. Note that there are
82 several steppings of the rate to run at different
83 maximum frequencies. Check the specs to make sure that your
84 particular processor can run at the rate you select here."
87 # Real-time clock/counter specifics
88 cdl_component CYGNUM_HAL_RTC_CONSTANTS {
89 display "Real-time clock constants"
93 cdl_option CYGNUM_HAL_RTC_NUMERATOR {
94 display "Real-time clock numerator"
98 cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
99 display "Real-time clock denominator"
103 This option selects the heartbeat rate for the real-time clock.
104 The rate is specified in ticks per second. Change this value
105 with caution - too high and your system will become saturated
106 just handling clock interrupts, too low and some operations
107 such as thread scheduling may become sluggish."
109 cdl_option CYGNUM_HAL_RTC_PERIOD {
110 display "Real-time clock period"
112 calculated (3686400/CYGNUM_HAL_RTC_DENOMINATOR) ;# Clock for OS Timer is 3.6864MHz
116 # Control over hardware layout.
117 cdl_interface CYGHWR_HAL_ARM_SOC_UART1 {
118 display "UART1 available as diagnostic/debug channel"
120 The chip has multiple serial channels which may be
121 used for different things on different platforms. This
122 interface allows a platform to indicate that the specified
123 serial port can be used as a diagnostic and/or debug channel."
126 cdl_interface CYGHWR_HAL_ARM_SOC_UART2 {
127 display "UART2 available as diagnostic/debug channel"
129 The chip has multiple serial channels which may be
130 used for different things on different platforms. This
131 interface allows a platform to indicate that the specified
132 serial port can be used as a diagnostic and/or debug channel."
135 cdl_interface CYGHWR_HAL_ARM_SOC_UART3 {
136 display "UART3 available as diagnostic/debug channel"
138 The chip has multiple serial channels which may be
139 used for different things on different platforms. This
140 interface allows a platform to indicate that the specified
141 serial port can be used as a diagnostic and/or debug channel."
144 cdl_interface CYGHWR_HAL_ARM_SOC_UART4 {
145 display "UART4 available as diagnostic/debug channel"
147 The chip has multiple serial channels which may be
148 used for different things on different platforms. This
149 interface allows a platform to indicate that the specified
150 serial port can be used as a diagnostic and/or debug channel."