1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: msalter
49 // Purpose: Intel XScale IXPD specific support routines
51 // Usage: #include <cyg/hal/hal_platform_setup.h>
52 // Only used by "vectors.S"
54 //####DESCRIPTIONEND####
56 //===========================================================================*/
58 #include <pkgconf/system.h> // System-wide configuration info
59 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
60 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
61 #include <cyg/hal/hal_ixp425.h> // Variant specific hardware definitions
62 #include <cyg/hal/hal_mmu.h> // MMU definitions
63 #include <cyg/hal/hal_mm.h> // more MMU definitions
64 #include <cyg/hal/ixdp425.h> // Platform specific hardware definitions
66 // ------------------------------------------------------------------------
67 // Convenience macros for setting up page table
69 .macro IXP_MAP_SDRAM va, c, b, x, p
70 XSCALE_MMU_SECTION SDRAM_PHYS_BASE>>20, \va>>20, SDRAM_SIZE>>20, \c, \b, 3, \x, \p
73 .macro IXP_MAP_EXP_V n, va, sz, c, b, x, p
74 XSCALE_MMU_SECTION (0x500 + ((IXP425_EXP_CS_SIZE * \n) >> 20)), \va>>20, \sz>>20, \c, \b, 3, \x, \p
77 .macro IXP_MAP_EXP n, sz, c, b, x, p
78 IXP_MAP_EXP_V \n, (0x50000000 + (IXP425_EXP_CS_SIZE * \n)), \sz, \c, \b, \x, \p
81 .macro IXP_MAP_IO addr, sz
82 XSCALE_MMU_SECTION \addr>>20, \addr>>20, \sz>>20, 0, 0, 3, 0, 0
86 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
87 #define PLATFORM_SETUP1 _platform_setup1
88 #define CYGHWR_HAL_ARM_HAS_MMU
90 // ------------------------------------------------------------------------
91 // Define macro used to diddle the LEDs during early initialization.
92 // Can use r0+r1. Argument in \x.
93 #define CYGHWR_LED_MACRO DISPLAY \x, r0, r1
96 .macro DELAY cycles, reg0
102 // ------------------------------------------------------------------------
103 // This macro represents the initial startup code for the platform
104 .macro _platform_setup1
106 #ifdef CYGHWR_HAL_ARM_BIGENDIAN
108 mrc p15, 0, r0, c1, c0, 0
110 mcr p15, 0, r0, c1, c0, 0
114 ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
117 // invalidate I & D caches & BTB
118 mcr p15, 0, r0, c7, c7, 0
121 // invalidate I & Data TLB
122 mcr p15, 0, r0, c8, c7, 0
125 // drain write and fill buffers
126 mcr p15, 0, r0, c7, c10, 4
129 // disable write buffer coalescing
130 mrc p15, 0, r0, c1, c0, 1
132 mcr p15, 0, r0, c1, c0, 1
135 // Setup chip selects
136 ldr r1, =IXP425_EXP_CFG_BASE
137 #ifdef IXP425_EXP_CS0_INIT
138 ldr r0, =IXP425_EXP_CS0_INIT
139 str r0, [r1, #IXP425_EXP_CS0]
141 #ifdef IXP425_EXP_CS1_INIT
142 ldr r0, =IXP425_EXP_CS1_INIT
143 str r0, [r1, #IXP425_EXP_CS1]
145 #ifdef IXP425_EXP_CS2_INIT
146 ldr r0, =IXP425_EXP_CS2_INIT
147 str r0, [r1, #IXP425_EXP_CS2]
149 #ifdef IXP425_EXP_CS3_INIT
150 ldr r0, =IXP425_EXP_CS3_INIT
151 str r0, [r1, #IXP425_EXP_CS3]
153 #ifdef IXP425_EXP_CS4_INIT
154 ldr r0, =IXP425_EXP_CS4_INIT
155 str r0, [r1, #IXP425_EXP_CS4]
157 #ifdef IXP425_EXP_CS5_INIT
158 ldr r0, =IXP425_EXP_CS5_INIT
159 str r0, [r1, #IXP425_EXP_CS5]
161 #ifdef IXP425_EXP_CS6_INIT
162 ldr r0, =IXP425_EXP_CS6_INIT
163 str r0, [r1, #IXP425_EXP_CS6]
165 #ifdef IXP425_EXP_CS7_INIT
166 ldr r0, =IXP425_EXP_CS7_INIT
167 str r0, [r1, #IXP425_EXP_CS7]
170 DISPLAY 0x1001, r7, r8
173 mrc p15, 0, r0, c1, c0, 0
174 orr r0, r0, #MMU_Control_I
175 mcr p15, 0, r0, c1, c0, 0
178 DISPLAY 0x1002, r7, r8
180 // Setup SDRAM controller
182 ldr r0, =IXP425_SDRAM_CFG_BASE
184 ldr r1, =IXP425_SDRAM_CONFIG_INIT
185 str r1, [r0, #IXP425_SDRAM_CONFIG]
187 // disable refresh cycles
189 str r1, [r0, #IXP425_SDRAM_REFRESH]
192 mov r1, #SDRAM_IR_NOP
193 str r1, [r0, #IXP425_SDRAM_IR]
196 // set SDRAM internal refresh val
197 ldr r1, =IXP425_SDRAM_REFRESH_CNT
198 str r1, [r0, #IXP425_SDRAM_REFRESH]
201 // send precharge-all command to close all open banks
202 mov r1, #SDRAM_IR_PRECHARGE
203 str r1, [r0, #IXP425_SDRAM_IR]
206 // provide 8 auto-refresh cycles
207 mov r1, #SDRAM_IR_AUTO_REFRESH
210 str r1, [r0, #IXP425_SDRAM_IR]
215 // set mode register in sdram
216 mov r1, #IXP425_SDRAM_SET_MODE_CMD
217 str r1, [r0, #IXP425_SDRAM_IR]
220 // start normal operation
221 mov r1, #SDRAM_IR_NORMAL
222 str r1, [r0, #IXP425_SDRAM_IR]
225 DISPLAY 0x1003, r7, r8
227 // Enable byte swapping control via page table P bit.
228 ldr r2, =IXP425_EXP_CFG_BASE
229 ldr r1, [r2, #IXP425_EXP_CNFG1]
230 orr r1, r1, #EXP_CNFG1_BYTE_SWAP_EN
231 str r1, [r2, #IXP425_EXP_CNFG1]
233 // value to load into pc to jump to real runtime address
235 #if defined(CYG_HAL_STARTUP_ROMRAM)
236 // R0 holds a RAM address for ROMRAM startup,
237 // so convert to a flash address.
238 orr r0, r0, #IXDP_FLASH_BASE
241 // Setup EXP_CNFG0 value to switch EXP bus out of low memory
242 ldr r2, =IXP425_EXP_CFG_BASE
243 ldr r1, [r2, #IXP425_EXP_CNFG0]
244 bic r1, r1, #EXP_CNFG0_MEM_MAP
246 ldr r4, =IXDP425_LED_DATA
252 // Here is where we switch from boot address (0x000000000) to the
253 // actual flash runtime address. We align to cache boundary so we
254 // execute from cache during the switchover. Cachelines are 8 words.
255 str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch
261 strh r3, [r4] // We should never reach this point. If we do,
262 // display FFFF and loop forever.
266 DISPLAY 0x1004, r7, r8
268 #if defined(CYG_HAL_STARTUP_ROMRAM)
269 mov r0, #IXDP_FLASH_BASE
270 mov r1, #SDRAM_PHYS_BASE
271 ldr r2, =__ram_data_end
277 // start executing from RAM
283 // Build mmu tables into RAM so page table walks by the cpu
284 // don't interfere with FLASH programming.
285 mov r1, #SDRAM_PHYS_BASE
286 orr r1, r1, #0x4000 // RAM tables
287 add r2, r1, #0x4000 // End of tables
296 // Build section mappings
297 IXP_MAP_SDRAM SDRAM_BASE, 1, 0, 0, 0 // Cached SDRAM
298 IXP_MAP_SDRAM SDRAM_ALIAS_BASE, 1, 0, 0, 0 // Cached SDRAM alias
299 IXP_MAP_SDRAM SDRAM_UNCACHED_BASE, 0, 0, 0, 0 // Uncached SDRAM
300 IXP_MAP_SDRAM SDRAM_DC_BASE, 1, 0, 0, 1 // Cached data coherent SDRAM
302 IXP_MAP_EXP 0, IXDP_FLASH_SIZE, 1, 0, 0, 0 // Flash
303 IXP_MAP_EXP 2, IXDP425_LED_SIZE, 0, 0, 0, 0 // LED
304 IXP_MAP_EXP 4, (1 << 20), 0, 0, 0, 0 // NPE use
305 IXP_MAP_EXP 5, (1 << 20), 0, 0, 0, 0 // NPE use
307 IXP_MAP_EXP_V 0, IXDP_FLASH_DC_BASE, IXDP_FLASH_SIZE, 1, 0, 0, 1 // data coherent flash
309 IXP_MAP_IO IXP425_PCI_WINDOW_BASE, IXP425_PCI_WINDOW_SIZE
310 IXP_MAP_IO IXP425_QMGR_BASE, IXP425_QMGR_SIZE
311 IXP_MAP_IO IXP425_PCI_CFG_BASE, IXP425_PCI_CFG_SIZE
312 IXP_MAP_IO IXP425_EXP_CFG_BASE, IXP425_EXP_CFG_SIZE
313 IXP_MAP_IO IXP425_MISC_CFG_BASE, IXP425_MISC_CFG_SIZE
314 IXP_MAP_IO IXP425_SDRAM_CFG_BASE, IXP425_SDRAM_CFG_SIZE
316 DISPLAY 0x1005, r7, r8
318 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
321 // Set the TTB register to DRAM mmu_table
322 ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables
323 mcr p15, 0, r0, c2, c0, 0 // load page table pointer
326 // enable permission checks in all domains
328 mcr p15, 0, r0, c3, c0, 0
331 DISPLAY 0x1006, r7, r8
334 mrc p15, 0, r0, c1, c0, 0
335 orr r0, r0, #MMU_Control_M
336 orr r0, r0, #MMU_Control_R
337 mcr p15, 0, r0, c1, c0, 0
340 DISPLAY 0x1007, r7, r8
343 mrc p15, 0, r0, c1, c0, 0
344 orr r0, r0, #MMU_Control_C
345 mcr p15, 0, r0, c1, c0, 0
348 DISPLAY 0x1008, r7, r8
350 // Enable branch target buffer
351 mrc p15, 0, r0, c1, c0, 0
352 orr r0, r0, #MMU_Control_BTB
353 mcr p15, 0, r0, c1, c0, 0
356 DISPLAY 0x1009, r7, r8
358 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
361 mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
364 mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
367 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
370 DISPLAY 0x100A, r7, r8
373 ldr r1, =hal_dram_size /* [see hal_intr.h] */
377 DISPLAY 0x100B, r7, r8
379 .endm // _platform_setup1
381 #else // defined(CYG_HAL_STARTUP_ROM)
382 #define PLATFORM_SETUP1
385 #define PLATFORM_VECTORS _platform_vectors
386 .macro _platform_vectors
389 /*---------------------------------------------------------------------------*/
390 /* end of hal_platform_setup.h */
391 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */