1 #ifndef CYGONCE_VAR_INTR_H
2 #define CYGONCE_VAR_INTR_H
3 //=============================================================================
7 // Variant HAL interrupt and clock support
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): Bob Koninckx
46 // Contributors:Bob Koninckx
48 // Purpose: Variant interrupt support
49 // Description: The macros defined here provide the HAL APIs for handling
50 // interrupts and the clock on the MPC5xx variant CPUs.
51 // Usage: Is included via the architecture interrupt header:
52 // #include <cyg/hal/hal_intr.h>
55 //####DESCRIPTIONEND####
57 //=============================================================================
59 #include <pkgconf/hal.h>
61 #include <cyg/hal/plf_intr.h>
63 #include <cyg/infra/cyg_type.h> // types
65 #include <cyg/hal/ppc_regs.h> // register definitions
67 #include <cyg/hal/hal_io.h> // io macros
68 #include <cyg/infra/cyg_ass.h> // CYG_FAIL
70 //-----------------------------------------------------------------------------
71 // Special IMB3 arbitration code
72 typedef struct t_hal_mpc5xx_arbitration_data {
75 cyg_uint32 (* arbiter)(CYG_ADDRWORD, CYG_ADDRWORD);
77 } hal_mpc5xx_arbitration_data;
80 hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data *adata);
82 externC hal_mpc5xx_arbitration_data *
83 hal_mpc5xx_remove_arbitration_isr(cyg_uint32 apriority);
85 //-----------------------------------------------------------------------------
88 // Additional exceptions on the MPC5xx CPUs
89 #define CYGNUM_HAL_VECTOR_RESERVED_F 15
90 #define CYGNUM_HAL_VECTOR_SW_EMUL 16
91 #define CYGNUM_HAL_VECTOR_RESERVED_11 17
92 #define CYGNUM_HAL_VECTOR_RESERVED_12 18
93 #define CYGNUM_HAL_VECTOR_ITLB_ERROR 19
94 #define CYGNUM_HAL_VECTOR_DTLB_ERROR 20
95 #define CYGNUM_HAL_VECTOR_RESERVED_15 21
96 #define CYGNUM_HAL_VECTOR_RESERVED_16 22
97 #define CYGNUM_HAL_VECTOR_RESERVED_17 23
98 #define CYGNUM_HAL_VECTOR_RESERVED_18 24
99 #define CYGNUM_HAL_VECTOR_RESERVED_19 25
100 #define CYGNUM_HAL_VECTOR_RESERVED_1A 26
101 #define CYGNUM_HAL_VECTOR_RESERVED_1B 27
102 #define CYGNUM_HAL_VECTOR_DATA_BP 28
103 #define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 29
104 #define CYGNUM_HAL_VECTOR_PERIPHERAL_BP 30
105 #define CYGNUM_HAL_VECTOR_NMI 31
107 #define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_NMI
109 // These are the values used when passed out to an
110 // external exception handler using cyg_hal_deliver_exception()
111 #define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0
112 #define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK
113 #define CYGNUM_HAL_EXCEPTION_RESERVED_3 CYGNUM_HAL_VECTOR_RESERVED_3
114 #define CYGNUM_HAL_EXCEPTION_RESERVED_4 CYGNUM_HAL_VECTOR_RESERVED_4
115 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS CYGNUM_HAL_VECTOR_ALIGNMENT
116 #define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE
117 #define CYGNUM_HAL_EXCEPTION_RESERVED_A CYGNUM_HAL_VECTOR_RESERVED_A
118 #define CYGNUM_HAL_EXCEPTION_RESERVED_B CYGNUM_HAL_VECTOR_RESERVED_B
119 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL
120 #define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE
121 #define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST
122 #define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F
123 #define CYGNUM_HAL_EXCEPTION_SW_EMUL CYGNUM_HAL_VECTOR_SW_EMUL
124 #define CYGNUM_HAL_EXCEPTION_RESERVED_11 CYGNUM_HAL_VECTOR_RESERVED_11
125 #define CYGNUM_HAL_EXCEPTION_RESERVED_12 CYGNUM_HAL_VECTOR_RESERVED_12
126 #define CYGNUM_HAL_EXCEPTION_CODE_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_ITLB_ERROR
127 #define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_DTLB_ERROR
128 #define CYGNUM_HAL_EXCEPTION_RESERVED_15 CYGNUM_HAL_VECTOR_RESERVED_15
129 #define CYGNUM_HAL_EXCEPTION_RESERVED_16 CYGNUM_HAL_VECTOR_RESERVED_16
130 #define CYGNUM_HAL_EXCEPTION_RESERVED_17 CYGNUM_HAL_VECTOR_RESERVED_17
131 #define CYGNUM_HAL_EXCEPTION_RESERVED_18 CYGNUM_HAL_VECTOR_RESERVED_18
132 #define CYGNUM_HAL_EXCEPTION_RESERVED_19 CYGNUM_HAL_VECTOR_RESERVED_19
133 #define CYGNUM_HAL_EXCEPTION_RESERVED_1A CYGNUM_HAL_VECTOR_RESERVED_1A
134 #define CYGNUM_HAL_EXCEPTION_RESERVED_1B CYGNUM_HAL_VECTOR_RESERVED_1B
135 #define CYGNUM_HAL_EXCEPTION_DATA_BP CYGNUM_HAL_VECTOR_DATA_BP
136 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_INSTRUCTION_BP
137 #define CYGNUM_HAL_EXCEPTION_PERIPHERAL_BP CYGNUM_HAL_VECTOR_PERIPHERAL_BP
138 #define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI
140 // decoded exception vectors (decoded program exception)
141 #define CYGNUM_HAL_EXCEPTION_TRAP (-1)
142 #define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION (-2)
143 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION (-3)
144 #define CYGNUM_HAL_EXCEPTION_FPU (-4)
146 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0
147 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_NMI
149 #define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
151 //-----------------------------------------------------------------------------
154 // The first level of external interrupts
155 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ0 1
156 #define CYGNUM_HAL_INTERRUPT_SIU_LVL0 2
157 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ1 3
158 #define CYGNUM_HAL_INTERRUPT_SIU_LVL1 4
159 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ2 5
160 #define CYGNUM_HAL_INTERRUPT_SIU_LVL2 6
161 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ3 7
162 #define CYGNUM_HAL_INTERRUPT_SIU_LVL3 8
163 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ4 9
164 #define CYGNUM_HAL_INTERRUPT_SIU_LVL4 10
165 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ5 11
166 #define CYGNUM_HAL_INTERRUPT_SIU_LVL5 12
167 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ6 13
168 #define CYGNUM_HAL_INTERRUPT_SIU_LVL6 14
169 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ7 15
170 #define CYGNUM_HAL_INTERRUPT_SIU_LVL7 16
172 // Further decoded interrupts
173 #define CYGNUM_HAL_INTERRUPT_SIU_TB_A 17 // Time base reference A
174 #define CYGNUM_HAL_INTERRUPT_SIU_TB_B 18 // Time base reference B
175 #define CYGNUM_HAL_INTERRUPT_SIU_PIT 19 // Periodic interrupt timer
176 #define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC 20 // Real time clock once per second
177 #define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR 21 // Real time clock alarm
178 #define CYGNUM_HAL_INTERRUPT_SIU_COL 22 // Change of lock of the PLL
180 // Even further decoded interrupts
181 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1 23 // QUADCA queue 1 completion
182 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1 24 // QUADCA queue 1 pause
183 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2 25 // QUADCA queue 2 completion
184 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2 26 // QUADCA queue 2 pause
185 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1 27 // QUADCB queue 1 completion
186 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1 28 // QUADCB queue 1 pause
187 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2 29 // QUADCB queue 2 completion
188 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2 30 // QUADCB queue 2 pause
189 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX 31 // SCI 0 transmit
190 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC 32 // SCI 0 transmit complete
191 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX 33 // SCI 0 receiver full
192 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE 34 // SCI 0 idle line detected
193 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX 35 // SCI 1 transmit
194 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC 36 // SCI 1 transmit complete
195 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX 37 // SCI 1 receiver full
196 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE 38 // SCI 1 idle line detected
197 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF 39 // SCI 1 RX Queue top half full
198 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF 40 // SCI 1 RX Queue bottom half full
199 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE 41 // SCI 1 TX Queue top half full
200 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE 42 // SCI 1 TX Queue bottom half full
201 #define CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI 43 // SPI finished
202 #define CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF 44 // SPI Mode fault
203 #define CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA 45 // SPI Halt Acknowledge
204 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF 46 // TOUCANA buss off
205 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR 47 // TOUCANA error
206 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU 48 // TOUCANA wake up
207 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0 49 // TOUCANA buffer 0
208 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1 50 // TOUCANA buffer 1
209 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2 51 // TOUCANA buffer 2
210 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3 52 // TOUCANA buffer 3
211 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4 53 // TOUCANA buffer 4
212 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5 54 // TOUCANA buffer 5
213 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6 55 // TOUCANA buffer 6
214 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7 56 // TOUCANA buffer 7
215 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8 57 // TOUCANA buffer 8
216 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9 58 // TOUCANA buffer 9
217 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10 59 // TOUCANA buffer 10
218 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11 60 // TOUCANA buffer 11
219 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12 61 // TOUCANA buffer 12
220 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13 62 // TOUCANA buffer 13
221 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14 63 // TOUCANA buffer 14
222 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15 64 // TOUCANA buffer 15
223 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF 65 // TOUCANB buss off
224 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR 66 // TOUCANB error
225 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU 67 // TOUCANB wake up
226 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0 68 // TOUCANB buffer 0
227 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1 69 // TOUCANB buffer 1
228 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2 70 // TOUCANB buffer 2
229 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3 71 // TOUCANB buffer 3
230 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4 72 // TOUCANB buffer 4
231 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5 73 // TOUCANB buffer 5
232 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6 74 // TOUCANB buffer 6
233 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7 75 // TOUCANB buffer 7
234 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8 76 // TOUCANB buffer 8
235 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9 77 // TOUCANB buffer 9
236 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10 78 // TOUCANB buffer 10
237 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11 79 // TOUCANB buffer 11
238 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12 80 // TOUCANB buffer 12
239 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13 81 // TOUCANB buffer 13
240 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14 82 // TOUCANB buffer 14
241 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15 83 // TOUCANB buffer 15
242 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0 84 // TPU A channel 0
243 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1 85 // TPU A channel 1
244 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2 86 // TPU A channel 2
245 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3 87 // TPU A channel 3
246 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4 88 // TPU A channel 4
247 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5 89 // TPU A channel 5
248 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6 90 // TPU A channel 6
249 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7 91 // TPU A channel 7
250 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8 92 // TPU A channel 8
251 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9 93 // TPU A channel 9
252 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10 94 // TPU A channel 10
253 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11 95 // TPU A channel 11
254 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12 96 // TPU A channel 12
255 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13 97 // TPU A channel 13
256 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14 98 // TPU A channel 14
257 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15 99 // TPU A channel 15
258 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0 100 // TPU B channel 0
259 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1 101 // TPU B channel 1
260 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2 102 // TPU B channel 2
261 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3 103 // TPU B channel 3
262 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4 104 // TPU B channel 4
263 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5 105 // TPU B channel 5
264 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6 106 // TPU B channel 6
265 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7 107 // TPU B channel 7
266 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8 108 // TPU B channel 8
267 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9 109 // TPU B channel 9
268 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10 110 // TPU B channel 10
269 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11 111 // TPU B channel 11
270 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12 112 // TPU B channel 12
271 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13 113 // TPU B channel 13
272 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14 114 // TPU B channel 14
273 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15 115 // TPU B channel 15
274 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0 116 // MIOS PWM0
275 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1 117 // MIOS PWM1
276 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2 118 // MIOS PWM2
277 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3 119 // MIOS PWM3
278 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6 120 // MIOS MCSM6
279 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11 121 // MIOS MDASM11
280 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12 122 // MIOS MDASM12
281 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13 123 // MIOS MDASM13
282 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14 124 // MIOS MDASM14
283 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15 125 // MIOS MDASM15
284 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16 126 // MIOS PWM16
285 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17 127 // MIOS PWM17
286 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18 128 // MIOS PWM18
287 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19 129 // MIOS PWM19
288 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22 130 // MIOS MCSM22
289 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27 131 // MIOS MDASM27
290 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28 132 // MIOS MDASM28
291 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29 133 // MIOS MDASM29
292 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30 134 // MIOS MDASM30
293 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31 135 // MIOS MDASM31
295 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_DECREMENTER
296 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31
298 #define CYGARC_SIU_PRIORITY_HIGH 7 // Maximum interrupt priority on SIU
299 #define CYGARC_SIU_PRIORITY_LOW 0 // Minimum interrupt priority on SIU
300 #define CYGARC_IMB3_PRIORITY_HIGH 31 // Maximum interrupt priority on IMB3
301 #define CYGARC_IMB3_PRIORITY_LOW 0 // Minimum interrupt priority on IMB3
304 //--------------------------------------------------------------------------
305 // Interrupt controller access
306 static __inline__ void
307 cyg_hal_interrupt_mask ( cyg_uint32 vector )
310 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
312 // SIU interrupt vectors
315 HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
316 simask &= ~(((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRM0)
317 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
318 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
321 case CYGNUM_HAL_INTERRUPT_SIU_TB_A :
323 // TimeBase A interrupt
326 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
327 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFAE);
328 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
329 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
330 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
333 case CYGNUM_HAL_INTERRUPT_SIU_TB_B :
335 // TimeBase B interrupt
338 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
339 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFBE);
340 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
341 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
342 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
345 case CYGNUM_HAL_INTERRUPT_SIU_PIT:
347 // Periodic Interrupt
350 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
351 piscr &= ~(CYGARC_REG_IMM_PISCR_PIE);
352 piscr &= ~(CYGARC_REG_IMM_PISCR_PS); // Prevent from clearing interrupt flag.
353 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
356 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
358 // Real Time Clock Second
361 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
362 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SIE);
363 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
364 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // Accidently. Just do what is asked.
365 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
368 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
370 // Real Time Clock Alarm
373 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
374 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALE);
375 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
376 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do what is asked.
377 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
381 case CYGNUM_HAL_INTERRUPT_SIU_COL:
383 // PLL change of lock
386 HAL_READ_UINT16 (CYGARC_REG_IMM_COLIR, colir);
387 colir &= ~(CYGARC_REG_IMM_COLIR_COLIE);
388 colir &= ~(CYGARC_REG_IMM_COLIR_COLIS); // Prevent from clearing interrupt flag accidently.
389 HAL_WRITE_UINT16 (CYGARC_REG_IMM_COLIR, colir);
393 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
397 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
398 quacr1 &= ~(CYGARC_REG_IMM_QUACR1_CIE1);
399 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
403 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
407 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
408 quacr1 &= ~(CYGARC_REG_IMM_QUACR1_PIE1);
409 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
413 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
417 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
418 quacr2 &= ~(CYGARC_REG_IMM_QUACR2_CIE2);
419 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
423 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
427 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
428 quacr2 &= ~(CYGARC_REG_IMM_QUACR2_PIE2);
429 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
433 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
437 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
438 quacr1 &= ~(CYGARC_REG_IMM_QUACR1_CIE1);
439 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
443 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
447 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
448 quacr1 &= ~(CYGARC_REG_IMM_QUACR1_PIE1);
449 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
453 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
457 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
458 quacr2 &= ~(CYGARC_REG_IMM_QUACR2_CIE2);
459 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
463 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
467 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
468 quacr2 &= ~(CYGARC_REG_IMM_QUACR2_PIE2);
469 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
473 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
477 HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
478 sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_TIE);
479 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
483 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
487 HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
488 sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_TCIE);
489 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
493 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
497 HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
498 sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_RIE);
499 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
503 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
507 HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
508 sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_ILIE);
509 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
513 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
517 HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
518 sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_TIE);
519 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
523 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
527 HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
528 sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_TCIE);
529 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
533 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
537 HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
538 sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_RIE);
539 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
543 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
547 HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
548 sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_ILIE);
549 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
553 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
557 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
558 qsci1cr &= ~(CYGARC_REG_IMM_QSCI1CR_QTHFI);
559 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
563 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
567 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
568 qsci1cr &= ~(CYGARC_REG_IMM_QSCI1CR_QBHFI);
569 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
573 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
577 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
578 qsci1cr &= ~(CYGARC_REG_IMM_QSCI1CR_QTHEI);
579 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
583 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
587 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
588 qsci1cr &= ~(CYGARC_REG_IMM_QSCI1CR_QBHEI);
589 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
593 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
597 HAL_READ_UINT16(CYGARC_REG_IMM_SPCR2, spcr2);
598 spcr2 &= ~(CYGARC_REG_IMM_SPCR2_SPIFIE);
599 HAL_WRITE_UINT16(CYGARC_REG_IMM_SPCR2, spcr2);
603 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF:
604 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA:
608 HAL_READ_UINT16(CYGARC_REG_IMM_SPCR3, spcr3);
609 spcr3 &= ~(CYGARC_REG_IMM_SPCR3_HMIE);
610 HAL_WRITE_UINT16(CYGARC_REG_IMM_SPCR3, spcr3);
614 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF:
618 HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
619 canctrl0 &= ~(CYGARC_REG_IMM_CANCTRL0_BOFFMSK);
620 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
624 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR:
628 HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
629 canctrl0 &= ~(CYGARC_REG_IMM_CANCTRL0_ERRMSK);
630 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
634 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU:
638 HAL_READ_UINT16(CYGARC_REG_IMM_TCNMCR_A, tcnmcr);
639 tcnmcr &= ~(CYGARC_REG_IMM_TCNMCR_WAKEMSK);
640 HAL_WRITE_UINT16(CYGARC_REG_IMM_TCNMCR_A, tcnmcr);
644 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0:
645 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1:
646 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2:
647 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3:
648 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4:
649 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5:
650 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6:
651 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7:
652 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8:
653 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9:
654 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10:
655 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11:
656 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12:
657 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13:
658 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14:
659 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15:
663 HAL_READ_UINT16(CYGARC_REG_IMM_IMASK_A, imask);
664 imask &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0));
665 HAL_WRITE_UINT16(CYGARC_REG_IMM_IMASK_A, imask);
669 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF:
673 HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
674 canctrl0 &= ~(CYGARC_REG_IMM_CANCTRL0_BOFFMSK);
675 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
679 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR:
683 HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
684 canctrl0 &= ~(CYGARC_REG_IMM_CANCTRL0_ERRMSK);
685 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
689 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU:
693 HAL_READ_UINT16(CYGARC_REG_IMM_TCNMCR_B, tcnmcr);
694 tcnmcr &= ~(CYGARC_REG_IMM_TCNMCR_WAKEMSK);
695 HAL_WRITE_UINT16(CYGARC_REG_IMM_TCNMCR_B, tcnmcr);
699 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0:
700 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1:
701 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2:
702 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3:
703 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4:
704 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5:
705 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6:
706 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7:
707 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8:
708 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9:
709 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10:
710 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11:
711 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12:
712 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13:
713 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14:
714 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15:
718 HAL_READ_UINT16(CYGARC_REG_IMM_IMASK_B, imask);
719 imask &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0));
720 HAL_WRITE_UINT16(CYGARC_REG_IMM_IMASK_B, imask);
724 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0:
725 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1:
726 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2:
727 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3:
728 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4:
729 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5:
730 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6:
731 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7:
732 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8:
733 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9:
734 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10:
735 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11:
736 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12:
737 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13:
738 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14:
739 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15:
743 HAL_READ_UINT16(CYGARC_REG_IMM_CIER_A, cier);
744 cier &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0));
745 HAL_WRITE_UINT16(CYGARC_REG_IMM_CIER_A, cier);
749 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0:
750 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1:
751 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2:
752 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3:
753 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4:
754 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5:
755 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6:
756 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7:
757 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8:
758 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9:
759 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10:
760 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11:
761 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12:
762 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13:
763 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14:
764 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15:
768 HAL_READ_UINT16(CYGARC_REG_IMM_CIER_B, cier);
769 cier &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0));
770 HAL_WRITE_UINT16(CYGARC_REG_IMM_CIER_B, cier);
774 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0:
778 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
779 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN0);
780 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
784 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1:
788 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
789 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN1);
790 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
794 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2:
798 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
799 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN2);
800 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
804 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3:
808 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
809 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN3);
810 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
814 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6:
818 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
819 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN6);
820 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
824 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11:
828 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
829 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN11);
830 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
834 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12:
838 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
839 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN12);
840 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
844 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13:
848 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
849 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN13);
850 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
854 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
858 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
859 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN14);
860 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
864 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
868 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
869 mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN15);
870 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
874 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
878 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
879 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN16);
880 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
884 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
888 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
889 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN17);
890 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
894 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
898 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
899 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN18);
900 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
904 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
908 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
909 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN19);
910 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
914 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
918 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
919 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN22);
920 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
924 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
928 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
929 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN27);
930 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
934 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
938 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
939 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN28);
940 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
944 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
948 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
949 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN29);
950 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
954 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
958 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
959 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN30);
960 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
964 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
968 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
969 mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN31);
970 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
975 CYG_FAIL("Unknown Interrupt!!!");
980 static __inline__ void
981 cyg_hal_interrupt_unmask ( cyg_uint32 vector )
984 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
986 // SIU interrupt vectors
989 HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
990 simask |= (((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRM0)
991 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
992 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
995 case CYGNUM_HAL_INTERRUPT_SIU_TB_A :
997 // TimeBase A interrupt
1000 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
1001 tbscr |= (CYGARC_REG_IMM_TBSCR_REFAE);
1002 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
1003 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
1004 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
1007 case CYGNUM_HAL_INTERRUPT_SIU_TB_B :
1009 // TimeBase B interrupt
1012 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
1013 tbscr |= (CYGARC_REG_IMM_TBSCR_REFBE);
1014 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
1015 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
1016 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
1019 case CYGNUM_HAL_INTERRUPT_SIU_PIT:
1021 // Periodic Interrupt
1024 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
1025 piscr |= (CYGARC_REG_IMM_PISCR_PIE);
1026 piscr &= ~(CYGARC_REG_IMM_PISCR_PS); // Prevent from clearing interrupt flag.
1027 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
1030 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
1032 // Real Time Clock Second
1035 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
1036 rtcsc |= (CYGARC_REG_IMM_RTCSC_SIE);
1037 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
1038 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do what is asdked.
1039 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
1042 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
1044 // Real Time Clock Alarm
1047 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
1048 rtcsc |= (CYGARC_REG_IMM_RTCSC_ALE);
1049 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
1050 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do what is asdked.
1051 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
1055 case CYGNUM_HAL_INTERRUPT_SIU_COL:
1057 // PLL change of lock
1060 HAL_READ_UINT16 (CYGARC_REG_IMM_COLIR, colir);
1061 colir |= (CYGARC_REG_IMM_COLIR_COLIE);
1062 colir &= ~(CYGARC_REG_IMM_COLIR_COLIS); // Prevent from clearing interrupt flag accidently.
1063 HAL_WRITE_UINT16 (CYGARC_REG_IMM_COLIR, colir);
1067 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
1071 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
1072 quacr1 |= (CYGARC_REG_IMM_QUACR1_CIE1);
1073 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
1077 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
1081 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
1082 quacr1 |= (CYGARC_REG_IMM_QUACR1_PIE1);
1083 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
1087 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
1091 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
1092 quacr2 |= (CYGARC_REG_IMM_QUACR2_CIE2);
1093 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
1097 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
1101 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
1102 quacr2 |= (CYGARC_REG_IMM_QUACR2_PIE2);
1103 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
1107 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
1111 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
1112 quacr1 |= (CYGARC_REG_IMM_QUACR1_CIE1);
1113 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
1117 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
1121 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
1122 quacr1 |= (CYGARC_REG_IMM_QUACR1_PIE1);
1123 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
1127 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
1131 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
1132 quacr2 |= (CYGARC_REG_IMM_QUACR2_CIE2);
1133 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
1137 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
1141 HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
1142 quacr2 |= (CYGARC_REG_IMM_QUACR2_PIE2);
1143 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
1147 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
1151 HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
1152 sccxr1 |= (CYGARC_REG_IMM_SCCxR1_TIE);
1153 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
1157 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
1161 HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
1162 sccxr1 |= (CYGARC_REG_IMM_SCCxR1_TCIE);
1163 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
1167 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
1171 HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
1172 sccxr1 |= (CYGARC_REG_IMM_SCCxR1_RIE);
1173 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
1177 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
1181 HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
1182 sccxr1 |= (CYGARC_REG_IMM_SCCxR1_ILIE);
1183 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
1187 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
1191 HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
1192 sccxr1 |= (CYGARC_REG_IMM_SCCxR1_TIE);
1193 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
1197 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
1201 HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
1202 sccxr1 |= (CYGARC_REG_IMM_SCCxR1_TCIE);
1203 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
1207 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
1211 HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
1212 sccxr1 |= (CYGARC_REG_IMM_SCCxR1_RIE);
1213 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
1217 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
1221 HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
1222 sccxr1 |= (CYGARC_REG_IMM_SCCxR1_ILIE);
1223 HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
1227 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
1231 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
1232 qsci1cr |= (CYGARC_REG_IMM_QSCI1CR_QTHFI);
1233 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
1237 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
1241 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
1242 qsci1cr |= (CYGARC_REG_IMM_QSCI1CR_QBHFI);
1243 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
1247 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
1251 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
1252 qsci1cr |= (CYGARC_REG_IMM_QSCI1CR_QTHEI);
1253 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
1257 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
1261 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
1262 qsci1cr |= (CYGARC_REG_IMM_QSCI1CR_QBHEI);
1263 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
1267 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
1271 HAL_READ_UINT16(CYGARC_REG_IMM_SPCR2, spcr2);
1272 spcr2 |= (CYGARC_REG_IMM_SPCR2_SPIFIE);
1273 HAL_WRITE_UINT16(CYGARC_REG_IMM_SPCR2, spcr2);
1277 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF:
1278 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA:
1282 HAL_READ_UINT16(CYGARC_REG_IMM_SPCR3, spcr3);
1283 spcr3 |= (CYGARC_REG_IMM_SPCR3_HMIE);
1284 HAL_WRITE_UINT16(CYGARC_REG_IMM_SPCR3, spcr3);
1288 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF:
1290 cyg_uint16 canctrl0;
1292 HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
1293 canctrl0 |= (CYGARC_REG_IMM_CANCTRL0_BOFFMSK);
1294 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
1298 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR:
1300 cyg_uint16 canctrl0;
1302 HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
1303 canctrl0 |= (CYGARC_REG_IMM_CANCTRL0_ERRMSK);
1304 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
1308 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU:
1312 HAL_READ_UINT16(CYGARC_REG_IMM_TCNMCR_A, tcnmcr);
1313 tcnmcr |= (CYGARC_REG_IMM_TCNMCR_WAKEMSK);
1314 HAL_WRITE_UINT16(CYGARC_REG_IMM_TCNMCR_A, tcnmcr);
1318 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0:
1319 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1:
1320 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2:
1321 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3:
1322 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4:
1323 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5:
1324 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6:
1325 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7:
1326 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8:
1327 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9:
1328 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10:
1329 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11:
1330 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12:
1331 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13:
1332 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14:
1333 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15:
1337 HAL_READ_UINT16(CYGARC_REG_IMM_IMASK_A, imask);
1338 imask |= (((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0));
1339 HAL_WRITE_UINT16(CYGARC_REG_IMM_IMASK_A, imask);
1343 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF:
1345 cyg_uint16 canctrl0;
1347 HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
1348 canctrl0 |= (CYGARC_REG_IMM_CANCTRL0_BOFFMSK);
1349 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
1353 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR:
1355 cyg_uint16 canctrl0;
1357 HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
1358 canctrl0 |= (CYGARC_REG_IMM_CANCTRL0_ERRMSK);
1359 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
1363 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU:
1367 HAL_READ_UINT16(CYGARC_REG_IMM_TCNMCR_B, tcnmcr);
1368 tcnmcr |= (CYGARC_REG_IMM_TCNMCR_WAKEMSK);
1369 HAL_WRITE_UINT16(CYGARC_REG_IMM_TCNMCR_B, tcnmcr);
1373 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0:
1374 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1:
1375 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2:
1376 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3:
1377 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4:
1378 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5:
1379 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6:
1380 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7:
1381 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8:
1382 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9:
1383 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10:
1384 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11:
1385 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12:
1386 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13:
1387 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14:
1388 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15:
1392 HAL_READ_UINT16(CYGARC_REG_IMM_IMASK_B, imask);
1393 imask |= (((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0));
1394 HAL_WRITE_UINT16(CYGARC_REG_IMM_IMASK_B, imask);
1398 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0:
1399 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1:
1400 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2:
1401 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3:
1402 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4:
1403 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5:
1404 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6:
1405 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7:
1406 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8:
1407 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9:
1408 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10:
1409 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11:
1410 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12:
1411 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13:
1412 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14:
1413 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15:
1417 HAL_READ_UINT16(CYGARC_REG_IMM_CIER_A, cier);
1418 cier |= (((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0));
1419 HAL_WRITE_UINT16(CYGARC_REG_IMM_CIER_A, cier);
1423 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0:
1424 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1:
1425 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2:
1426 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3:
1427 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4:
1428 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5:
1429 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6:
1430 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7:
1431 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8:
1432 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9:
1433 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10:
1434 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11:
1435 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12:
1436 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13:
1437 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14:
1438 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15:
1442 HAL_READ_UINT16(CYGARC_REG_IMM_CIER_B, cier);
1443 cier |= (((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0));
1444 HAL_WRITE_UINT16(CYGARC_REG_IMM_CIER_B, cier);
1448 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0:
1450 cyg_uint16 mios1er0;
1452 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1453 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN0);
1454 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1458 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1:
1460 cyg_uint16 mios1er0;
1462 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1463 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN1);
1464 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1468 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2:
1470 cyg_uint16 mios1er0;
1472 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1473 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN2);
1474 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1478 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3:
1480 cyg_uint16 mios1er0;
1482 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1483 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN3);
1484 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1488 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6:
1490 cyg_uint16 mios1er0;
1492 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1493 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN6);
1494 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1498 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11:
1500 cyg_uint16 mios1er0;
1502 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1503 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN11);
1504 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1508 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12:
1510 cyg_uint16 mios1er0;
1512 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1513 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN12);
1514 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1518 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13:
1520 cyg_uint16 mios1er0;
1522 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1523 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN13);
1524 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1528 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
1530 cyg_uint16 mios1er0;
1532 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1533 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN14);
1534 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1538 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
1540 cyg_uint16 mios1er0;
1542 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1543 mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN15);
1544 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
1548 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
1550 cyg_uint16 mios1er1;
1552 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1553 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN16);
1554 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1558 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
1560 cyg_uint16 mios1er1;
1562 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1563 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN17);
1564 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1568 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
1570 cyg_uint16 mios1er1;
1572 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1573 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN18);
1574 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1578 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
1580 cyg_uint16 mios1er1;
1582 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1583 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN19);
1584 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1588 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
1590 cyg_uint16 mios1er1;
1592 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1593 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN22);
1594 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1598 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
1600 cyg_uint16 mios1er1;
1602 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1603 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN27);
1604 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1608 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
1610 cyg_uint16 mios1er1;
1612 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1613 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN28);
1614 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1618 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
1620 cyg_uint16 mios1er1;
1622 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1623 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN29);
1624 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1628 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
1630 cyg_uint16 mios1er1;
1632 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1633 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN30);
1634 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1638 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
1640 cyg_uint16 mios1er1;
1642 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1643 mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN31);
1644 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
1649 CYG_FAIL("Unknown Interrupt!!!");
1654 static __inline__ void
1655 cyg_hal_interrupt_acknowledge ( cyg_uint32 vector )
1658 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
1660 // SIU interrupt vectors
1663 // When IRQx is configured as an edge interrupt it needs to be
1664 // cleared. Write to INTx and IRQ/level bits are ignore so
1665 // it's safe to do always.
1666 HAL_READ_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
1667 sipend |= (((cyg_uint32) CYGARC_REG_IMM_SIPEND_IRQ0)
1668 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
1669 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
1673 case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
1675 // TimeBase A interrupt
1678 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
1679 tbscr |= CYGARC_REG_IMM_TBSCR_REFA;
1680 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // Only acknowledge the requested one
1681 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
1685 case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
1687 // TimeBase B interrupt
1690 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
1691 tbscr |= CYGARC_REG_IMM_TBSCR_REFB;
1692 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Only acknowledge the requested one.
1693 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
1697 case CYGNUM_HAL_INTERRUPT_SIU_PIT:
1699 // Periodic Interrupt
1702 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
1703 piscr |= CYGARC_REG_IMM_PISCR_PS;
1704 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
1708 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
1710 // Real Time Clock Second
1713 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
1714 rtcsc |= CYGARC_REG_IMM_RTCSC_SEC;
1715 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // Only acknowledge the requested one
1716 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
1720 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
1722 // Real Time Clock Alarm
1725 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
1726 rtcsc |= CYGARC_REG_IMM_RTCSC_ALR;
1727 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Only acknowledge the requested one
1728 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
1732 case CYGNUM_HAL_INTERRUPT_SIU_COL:
1736 HAL_READ_UINT16(CYGARC_REG_IMM_COLIR, colir);
1737 colir |= CYGARC_REG_IMM_COLIR_COLIS;
1738 HAL_WRITE_UINT16(CYGARC_REG_IMM_COLIR, colir);
1742 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
1746 HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
1747 quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF1);
1748 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
1752 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
1756 HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
1757 quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF1);
1758 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
1762 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
1766 HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
1767 quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF2);
1768 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
1772 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
1776 HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
1777 quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF2);
1778 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
1782 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
1786 HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
1787 quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF1);
1788 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
1792 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
1796 HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
1797 quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF1);
1798 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
1802 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
1806 HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
1807 quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF2);
1808 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
1812 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
1816 HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
1817 quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF2);
1818 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
1822 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
1823 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
1824 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
1825 // Nothing needs to be done here
1828 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
1832 HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, scxsr);
1833 scxsr &= ~(CYGARC_REG_IMM_SCxSR_IDLE);
1834 HAL_WRITE_UINT16(CYGARC_REG_IMM_SC1SR, scxsr);
1838 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
1839 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
1840 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
1841 // nothing needs to be done here
1844 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
1848 HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, scxsr);
1849 scxsr &= ~(CYGARC_REG_IMM_SCxSR_IDLE);
1850 HAL_WRITE_UINT16(CYGARC_REG_IMM_SC2SR, scxsr);
1854 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
1858 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
1859 qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHF);
1860 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
1864 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
1868 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
1869 qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QBHF);
1870 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
1874 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
1878 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
1879 qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHE);
1880 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
1884 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
1888 HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
1889 qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QBHE);
1890 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
1894 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
1898 HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, spsr);
1899 spsr &= ~(CYGARC_REG_IMM_SPSR_SPIF);
1900 HAL_WRITE_UINT16(CYGARC_REG_IMM_SPSR, spsr);
1904 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF:
1908 HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, spsr);
1909 spsr &= ~(CYGARC_REG_IMM_SPSR_MODF);
1910 HAL_WRITE_UINT16(CYGARC_REG_IMM_SPSR, spsr);
1914 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA:
1918 HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, spsr);
1919 spsr &= ~(CYGARC_REG_IMM_SPSR_HALTA);
1920 HAL_WRITE_UINT16(CYGARC_REG_IMM_SPSR, spsr);
1924 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF:
1928 HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // Read the flag as a one
1929 estat &= ~(CYGARC_REG_IMM_ESTAT_BOFFINT);
1930 HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // And write it as a zero
1934 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR:
1938 HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // Read the flag as a one
1939 estat &= ~(CYGARC_REG_IMM_ESTAT_ERRINT);
1940 HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // And write it as a zero
1944 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU:
1948 HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // Read tthe flag as a one
1949 estat &= ~(CYGARC_REG_IMM_ESTAT_WAKEINT);
1950 HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // And write it as a zero
1954 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0:
1955 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1:
1956 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2:
1957 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3:
1958 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4:
1959 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5:
1960 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6:
1961 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7:
1962 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8:
1963 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9:
1964 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10:
1965 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11:
1966 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12:
1967 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13:
1968 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14:
1969 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15:
1973 HAL_READ_UINT16(CYGARC_REG_IMM_IFLAG_A, iflag); // Read the flag as a one
1974 iflag &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0));
1975 HAL_WRITE_UINT16(CYGARC_REG_IMM_IFLAG_A, iflag); // And write it as a zero
1979 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF:
1983 HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // Read the flag as a one
1984 estat &= ~(CYGARC_REG_IMM_ESTAT_BOFFINT);
1985 HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // And write it as a zero
1989 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR:
1993 HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // Read the flag as a one
1994 estat &= ~(CYGARC_REG_IMM_ESTAT_ERRINT);
1995 HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // And write it as a zero
1999 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU:
2003 HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // Read the flag as a one
2004 estat &= ~(CYGARC_REG_IMM_ESTAT_WAKEINT);
2005 HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // And write it as a zero
2009 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0:
2010 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1:
2011 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2:
2012 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3:
2013 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4:
2014 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5:
2015 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6:
2016 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7:
2017 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8:
2018 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9:
2019 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10:
2020 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11:
2021 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12:
2022 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13:
2023 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14:
2024 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15:
2028 HAL_READ_UINT16(CYGARC_REG_IMM_IFLAG_B, iflag); // Read the flag as a one
2029 iflag &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0));
2030 HAL_WRITE_UINT16(CYGARC_REG_IMM_IFLAG_B, iflag); // And write it as a zero
2034 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0:
2035 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1:
2036 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2:
2037 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3:
2038 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4:
2039 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5:
2040 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6:
2041 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7:
2042 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8:
2043 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9:
2044 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10:
2045 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11:
2046 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12:
2047 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13:
2048 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14:
2049 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15:
2053 HAL_READ_UINT16(CYGARC_REG_IMM_CISR_A, cisr);
2054 cisr &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0));
2055 HAL_WRITE_UINT16(CYGARC_REG_IMM_CISR_A, cisr);
2059 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0:
2060 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1:
2061 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2:
2062 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3:
2063 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4:
2064 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5:
2065 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6:
2066 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7:
2067 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8:
2068 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9:
2069 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10:
2070 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11:
2071 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12:
2072 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13:
2073 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14:
2074 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15:
2078 HAL_READ_UINT16(CYGARC_REG_IMM_CISR_B, cisr);
2079 cisr &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0));
2080 HAL_WRITE_UINT16(CYGARC_REG_IMM_CISR_B, cisr);
2084 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0:
2086 cyg_uint16 mios1sr0;
2088 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2089 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL0);
2090 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2094 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1:
2096 cyg_uint16 mios1sr0;
2098 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2099 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL1);
2100 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2104 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2:
2106 cyg_uint16 mios1sr0;
2108 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2109 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL2);
2110 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2114 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3:
2116 cyg_uint16 mios1sr0;
2118 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2119 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL3);
2120 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2124 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6:
2126 cyg_uint16 mios1sr0;
2128 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2129 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL6);
2130 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2134 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11:
2136 cyg_uint16 mios1sr0;
2138 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2139 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL11);
2140 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2144 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12:
2146 cyg_uint16 mios1sr0;
2148 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2149 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL12);
2150 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2154 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13:
2156 cyg_uint16 mios1sr0;
2158 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2159 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL13);
2160 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2164 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
2166 cyg_uint16 mios1sr0;
2168 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2169 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL14);
2170 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2174 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
2176 cyg_uint16 mios1sr0;
2178 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2179 mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL15);
2180 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
2184 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
2186 cyg_uint16 mios1sr1;
2188 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2189 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL16);
2190 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2194 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
2196 cyg_uint16 mios1sr1;
2198 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2199 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL17);
2200 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2204 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
2206 cyg_uint16 mios1sr1;
2208 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2209 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL18);
2210 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2214 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
2216 cyg_uint16 mios1sr1;
2218 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2219 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL19);
2220 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2224 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
2226 cyg_uint16 mios1sr1;
2228 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2229 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL22);
2230 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2234 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
2236 cyg_uint16 mios1sr1;
2238 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2239 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL27);
2240 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2244 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
2246 cyg_uint16 mios1sr1;
2248 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2249 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL28);
2250 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2254 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
2256 cyg_uint16 mios1sr1;
2258 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2259 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL29);
2260 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2264 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
2266 cyg_uint16 mios1sr1;
2268 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2269 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL30);
2270 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2274 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
2276 cyg_uint16 mios1sr1;
2278 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2279 mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL31);
2280 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
2286 CYG_FAIL("Unknown Interrupt!!!");
2291 static __inline__ void
2292 cyg_hal_interrupt_configure ( cyg_uint32 vector,
2297 // Only external interrupts can be fully configured in the true meaning of the word
2298 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0:
2299 case CYGNUM_HAL_INTERRUPT_SIU_IRQ1:
2300 case CYGNUM_HAL_INTERRUPT_SIU_IRQ2:
2301 case CYGNUM_HAL_INTERRUPT_SIU_IRQ3:
2302 case CYGNUM_HAL_INTERRUPT_SIU_IRQ4:
2303 case CYGNUM_HAL_INTERRUPT_SIU_IRQ5:
2304 case CYGNUM_HAL_INTERRUPT_SIU_IRQ6:
2305 case CYGNUM_HAL_INTERRUPT_SIU_IRQ7:
2307 // External interrupts
2308 cyg_uint32 siel, bit;
2310 CYG_ASSERT( level || !up, "Only falling edge is supported");
2312 bit = (((cyg_uint32) CYGARC_REG_IMM_SIEL_ED0)
2313 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
2315 HAL_READ_UINT32 (CYGARC_REG_IMM_SIEL, siel);
2318 // Set edge detect bit.
2321 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIEL, siel);
2325 // Attempts to configure all other interrupt sources should fail
2327 CYG_FAIL("Unknown Interrupt!!!");
2332 static __inline__ void
2333 cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level )
2335 if(vector < CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1)
2337 // Note: highest priority has the lowest numerical value.
2338 CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_LOW, "Invalid priority");
2339 CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority");
2343 CYG_ASSERT( level >= CYGARC_IMB3_PRIORITY_LOW, "Invalid priority");
2344 CYG_ASSERT( level <= CYGARC_IMB3_PRIORITY_HIGH, "Invalid priority");
2348 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
2349 // These cannot be configured.
2352 case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
2353 case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
2355 // TimeBase A+B interrupt
2358 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
2359 tbscr &= ~(CYGARC_REG_IMM_TBSCR_IRQMASK);
2360 tbscr |= CYGARC_REG_IMM_TBSCR_IRQ0 >> level;
2361 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent fom clearing interrupt flags
2362 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
2363 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
2367 case CYGNUM_HAL_INTERRUPT_SIU_PIT:
2369 // Periodic Interrupt
2372 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
2373 piscr &= ~(CYGARC_REG_IMM_PISCR_IRQMASK);
2374 piscr |= CYGARC_REG_IMM_PISCR_IRQ0 >> level;
2375 piscr &= ~(CYGARC_REG_IMM_PISCR_PS); // Prevent from clearing interrupt flag.
2376 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
2380 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
2381 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
2383 // Real Time Clock Second & Real Time Clock Alarm
2386 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
2387 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_IRQMASK);
2388 rtcsc |= CYGARC_REG_IMM_RTCSC_IRQ0 >> level;
2389 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
2390 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do wahat is asked.
2391 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
2395 case CYGNUM_HAL_INTERRUPT_SIU_COL:
2399 HAL_READ_UINT16(CYGARC_REG_IMM_COLIR, colir);
2400 colir &= ~(CYGARC_REG_IMM_COLIR_COLIRQ); // mask out the level
2401 colir |= CYGARC_REG_IMM_COLIR_IRQ0 >> level; // and set the new level
2402 colir &= ~(CYGARC_REG_IMM_COLIR_COLIS); // Prevent from clearing interrupt flag accidently.
2403 HAL_WRITE_UINT16(CYGARC_REG_IMM_COLIR, colir);
2407 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
2408 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
2410 cyg_uint16 quadc64int;
2411 cyg_uint16 the_level = level << CYGARC_REG_IMM_QUADC64INT_IRL1_SHIFT;
2413 HAL_READ_UINT16(CYGARC_REG_IMM_QUADC64INT_A, quadc64int);
2414 quadc64int &= ~(CYGARC_REG_IMM_QUADC64INT_IRL1);
2415 quadc64int |= the_level;
2416 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUADC64INT_A, quadc64int);
2420 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
2421 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
2423 cyg_uint16 quadc64int;
2424 cyg_uint16 the_level = level << CYGARC_REG_IMM_QUADC64INT_IRL2_SHIFT;
2426 HAL_READ_UINT16(CYGARC_REG_IMM_QUADC64INT_A, quadc64int);
2427 quadc64int &= ~(CYGARC_REG_IMM_QUADC64INT_IRL2);
2428 quadc64int |= the_level;
2429 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUADC64INT_A, quadc64int);
2433 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
2434 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
2436 cyg_uint16 quadc64int;
2437 cyg_uint16 the_level = level << CYGARC_REG_IMM_QUADC64INT_IRL1_SHIFT;
2439 HAL_READ_UINT16(CYGARC_REG_IMM_QUADC64INT_B, quadc64int);
2440 quadc64int &= ~(CYGARC_REG_IMM_QUADC64INT_IRL1);
2441 quadc64int |= the_level;
2442 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUADC64INT_B, quadc64int);
2446 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
2447 case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
2449 cyg_uint16 quadc64int;
2450 cyg_uint16 the_level = level << CYGARC_REG_IMM_QUADC64INT_IRL2_SHIFT;
2452 HAL_READ_UINT16(CYGARC_REG_IMM_QUADC64INT_B, quadc64int);
2453 quadc64int &= ~(CYGARC_REG_IMM_QUADC64INT_IRL2);
2454 quadc64int |= the_level;
2455 HAL_WRITE_UINT16(CYGARC_REG_IMM_QUADC64INT_B, quadc64int);
2459 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
2460 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
2461 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
2462 case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
2463 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
2464 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
2465 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
2466 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
2467 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
2468 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
2469 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
2470 case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
2472 cyg_uint16 qdsci_il;
2473 cyg_uint16 the_level = level << CYGARC_REG_IMM_QDSCI_IL_ILDSCI_SHIFT;
2475 HAL_READ_UINT16(CYGARC_REG_IMM_QDSCI_IL, qdsci_il);
2476 qdsci_il &= ~(CYGARC_REG_IMM_QDSCI_IL_ILDSCI);
2477 qdsci_il |= the_level;
2478 HAL_WRITE_UINT16(CYGARC_REG_IMM_QDSCI_IL, qdsci_il);
2482 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
2483 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF:
2484 case CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA:
2487 cyg_uint16 the_level = level << CYGARC_REG_IMM_QSPI_IL_ILQSPI_SHIFT;
2489 HAL_READ_UINT16(CYGARC_REG_IMM_QSPI_IL, qspi_il);
2490 qspi_il &= ~(CYGARC_REG_IMM_QSPI_IL_ILQSPI);
2491 qspi_il |= the_level;
2492 HAL_WRITE_UINT16(CYGARC_REG_IMM_QSPI_IL, qspi_il);
2496 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF:
2497 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR:
2498 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU:
2499 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0:
2500 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1:
2501 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2:
2502 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3:
2503 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4:
2504 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5:
2505 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6:
2506 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7:
2507 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8:
2508 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9:
2509 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10:
2510 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11:
2511 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12:
2512 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13:
2513 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14:
2514 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15:
2516 cyg_uint16 irl = (level % 8) << CYGARC_REG_IMM_CANICR_IRL_SHIFT;
2517 cyg_uint16 ilsb = (level / 8) << CYGARC_REG_IMM_CANICR_ILBS_SHIFT;
2520 HAL_READ_UINT16(CYGARC_REG_IMM_CANICR_A, canicr);
2521 canicr &= ~(CYGARC_REG_IMM_CANICR_IRL);
2522 canicr &= ~(CYGARC_REG_IMM_CANICR_ILBS);
2525 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANICR_A, canicr);
2529 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF:
2530 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR:
2531 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU:
2532 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0:
2533 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1:
2534 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2:
2535 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3:
2536 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4:
2537 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5:
2538 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6:
2539 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7:
2540 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8:
2541 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9:
2542 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10:
2543 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11:
2544 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12:
2545 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13:
2546 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14:
2547 case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15:
2549 cyg_uint16 irl = (level % 8) << CYGARC_REG_IMM_CANICR_IRL_SHIFT;
2550 cyg_uint16 ilsb = (level / 8) << CYGARC_REG_IMM_CANICR_ILBS_SHIFT;
2553 HAL_READ_UINT16(CYGARC_REG_IMM_CANICR_B, canicr);
2554 canicr &= ~(CYGARC_REG_IMM_CANICR_IRL);
2555 canicr &= ~(CYGARC_REG_IMM_CANICR_ILBS);
2558 HAL_WRITE_UINT16(CYGARC_REG_IMM_CANICR_B, canicr);
2562 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0:
2563 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1:
2564 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2:
2565 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3:
2566 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4:
2567 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5:
2568 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6:
2569 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7:
2570 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8:
2571 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9:
2572 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10:
2573 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11:
2574 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12:
2575 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13:
2576 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14:
2577 case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15:
2579 cyg_uint16 cirl = (level % 8) << CYGARC_REG_IMM_TICR_CIRL_SHIFT;
2580 cyg_uint16 ilsb = (level / 8) << CYGARC_REG_IMM_TICR_ILBS_SHIFT;
2583 HAL_READ_UINT16(CYGARC_REG_IMM_TICR_A, ticr);
2584 ticr &= ~(CYGARC_REG_IMM_TICR_CIRL);
2585 ticr &= ~(CYGARC_REG_IMM_TICR_ILBS);
2588 HAL_WRITE_UINT16(CYGARC_REG_IMM_TICR_A, ticr);
2592 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0:
2593 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1:
2594 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2:
2595 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3:
2596 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4:
2597 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5:
2598 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6:
2599 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7:
2600 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8:
2601 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9:
2602 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10:
2603 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11:
2604 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12:
2605 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13:
2606 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14:
2607 case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15:
2609 cyg_uint16 cirl = (level % 8) << CYGARC_REG_IMM_TICR_CIRL_SHIFT;
2610 cyg_uint16 ilsb = (level / 8) << CYGARC_REG_IMM_TICR_ILBS_SHIFT;
2613 HAL_READ_UINT16(CYGARC_REG_IMM_TICR_B, ticr);
2614 ticr &= ~(CYGARC_REG_IMM_TICR_CIRL);
2615 ticr &= ~(CYGARC_REG_IMM_TICR_ILBS);
2618 HAL_WRITE_UINT16(CYGARC_REG_IMM_TICR_B, ticr);
2622 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0:
2623 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1:
2624 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2:
2625 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3:
2626 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6:
2627 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11:
2628 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12:
2629 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13:
2630 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
2631 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
2633 cyg_uint16 lvl = (level % 8) << CYGARC_REG_IMM_MIOS1LVL_LVL_SHIFT;
2634 cyg_uint16 tm = (level / 8) << CYGARC_REG_IMM_MIOS1LVL_TM_SHIFT;
2635 cyg_uint16 mios1lvl;
2637 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1LVL0, mios1lvl);
2638 mios1lvl &= ~(CYGARC_REG_IMM_MIOS1LVL_LVL);
2639 mios1lvl &= ~(CYGARC_REG_IMM_MIOS1LVL_TM);
2642 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1LVL0, mios1lvl);
2646 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
2647 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
2648 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
2649 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
2650 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
2651 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
2652 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
2653 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
2654 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
2655 case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
2657 cyg_uint16 lvl = (level % 8) << CYGARC_REG_IMM_MIOS1LVL_LVL_SHIFT;
2658 cyg_uint16 tm = (level / 8) << CYGARC_REG_IMM_MIOS1LVL_TM_SHIFT;
2659 cyg_uint16 mios1lvl;
2661 HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1LVL1, mios1lvl);
2662 mios1lvl &= ~(CYGARC_REG_IMM_MIOS1LVL_LVL);
2663 mios1lvl &= ~(CYGARC_REG_IMM_MIOS1LVL_TM);
2666 HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1LVL1, mios1lvl);
2671 CYG_FAIL("Unknown Interrupt!!!");
2676 // The decrementer interrupt cannnot be masked, configured or acknowledged.
2678 #define HAL_INTERRUPT_MASK( _vector_ ) \
2680 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
2681 cyg_hal_interrupt_mask ( (_vector_) ); \
2684 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
2686 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
2687 cyg_hal_interrupt_unmask ( (_vector_) ); \
2690 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
2692 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
2693 cyg_hal_interrupt_acknowledge ( (_vector_) ); \
2696 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
2698 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
2699 cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) ); \
2702 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
2704 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
2705 cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \
2708 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
2710 //--------------------------------------------------------------------------
2711 // Interrupt arbiters
2712 externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector,
2714 externC cyg_uint32 hal_arbitration_isr_pit (CYG_ADDRWORD vector,
2716 externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector,
2718 externC cyg_uint32 hal_arbitration_isr_sci (CYG_ADDRWORD vector,
2721 //-----------------------------------------------------------------------------
2722 // Symbols used by assembly code
2723 #define CYGARC_VARIANT_DEFS \
2724 DEFINE(CYGNUM_HAL_VECTOR_NMI, CYGNUM_HAL_VECTOR_NMI);
2726 //-----------------------------------------------------------------------------
2727 // Interrupt source priorities
2728 // Maybe this is not the best way to do this. Fact remains that these priorities
2729 // are not hard wired by the board layout, but are all software configurable. Not
2730 // so easy to combine flexibility with generality
2731 #define CYGNUM_HAL_INTERRUPT_SIU_TB_A_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TB
2732 #define CYGNUM_HAL_INTERRUPT_SIU_TB_B_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TB
2733 #define CYGNUM_HAL_INTERRUPT_SIU_PIT_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_PIT
2734 #define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_RTC
2735 #define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_RTC
2736 #define CYGNUM_HAL_INTERRUPT_SIU_COL_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_PLL
2737 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE1
2738 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE1
2739 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE2
2740 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE2
2741 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE1
2742 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE1
2743 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE2
2744 #define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE2
2745 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2746 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2747 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2748 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2749 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2750 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2751 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2752 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2753 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2754 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2755 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2756 #define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
2757 #define CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSPI
2758 #define CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSPI
2759 #define CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSPI
2760 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2761 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2762 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2763 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2764 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2765 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2766 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2767 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2768 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2769 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2770 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2771 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2772 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2773 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2774 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2775 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2776 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2777 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2778 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
2779 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2780 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2781 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2782 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2783 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2784 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2785 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2786 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2787 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2788 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2789 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2790 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2791 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2792 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2793 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2794 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2795 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2796 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2797 #define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
2798 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2799 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2800 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2801 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2802 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2803 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2804 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2805 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2806 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2807 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2808 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2809 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2810 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2811 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2812 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2813 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
2814 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2815 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2816 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2817 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2818 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2819 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2820 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2821 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2822 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2823 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2824 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2825 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2826 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2827 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2828 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2829 #define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
2830 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2831 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2832 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2833 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2834 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2835 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2836 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2837 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2838 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2839 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
2840 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2841 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2842 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2843 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2844 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2845 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2846 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2847 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2848 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2849 #define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
2851 //-----------------------------------------------------------------------------
2852 #endif // ifndef CYGONCE_VAR_INTR_H
2853 // End of var_intr.h