1 #ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H
2 #define CYGONCE_HAL_PPC_QUICC_PPC8XX_H
4 //==========================================================================
8 // PowerPC QUICC register definitions
10 //==========================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2002, 2003 Gary Thomas
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
41 // at http://sources.redhat.com/ecos/ecos-license/
42 // -------------------------------------------
43 //####ECOSGPLCOPYRIGHTEND####
44 //==========================================================================
45 //#####DESCRIPTIONBEGIN####
50 // Purpose: Provide PPC QUICC definitions
51 // Description: Provide PPC QUICC definitions
52 // Usage: THIS IS NOT AN EXTERNAL API
53 // This file is in the include dir to share it between
54 // QUICC serial code and MBX initialization code.
55 // #include <cyg/hal/quicc/ppc8xx.h>
59 //####DESCRIPTIONEND####
61 //==========================================================================
65 #define SIUMCR 0x000 /* SIU Module configuration */
66 #define SYPCR 0x004 /* SIU System Protection Control */
67 #define SIPEND 0x010 /* SIU Interrupt Pending Register */
68 #define SIMASK 0x014 /* SIU Interrupt MASK Register */
69 #define SIEL 0x018 /* SIU Interrupt Edge/Level Register */
70 #define SIVEC 0x01C /* SIU Interrupt Vector Register */
71 #define SDCR 0x030 /* SDMA Config Register */
72 #define BR0 0x100 /* Base Register 0 */
73 #define OR0 0x104 /* Option Register 0 */
74 #define BR1 0x108 /* Base Register 1 */
75 #define OR1 0x10C /* Option Register 1 */
76 #define BR2 0x110 /* Base Register 2 */
77 #define OR2 0x114 /* Option Register 2 */
78 #define BR3 0x118 /* Base Register 2 */
79 #define OR3 0x11C /* Option Register 2 */
80 #define BR4 0x120 /* Base Register 2 */
81 #define OR4 0x124 /* Option Register 2 */
82 #define BR5 0x128 /* Base Register 2 */
83 #define OR5 0x12C /* Option Register 2 */
84 #define BR6 0x130 /* Base Register 2 */
85 #define OR6 0x134 /* Option Register 2 */
86 #define BR7 0x138 /* Base Register 2 */
87 #define OR7 0x13C /* Option Register 2 */
88 #define MAR 0x164 /* Memory Address */
89 #define MCR 0x168 /* Memory Command */
90 #define MAMR 0x170 /* Machine A Mode Register */
91 #define MBMR 0x174 /* Machine B Mode Register */
92 #define MPTPR 0x17A /* Memory Periodic Timer Prescaler */
93 #define MDR 0x17C /* Memory Data */
94 #define TBSCR 0x200 /* Time Base Status and Control Register */
95 #define RTCSC 0x220 /* Real Timer Clock Status and Control */
96 #define PISCR 0x240 /* PIT Status and Control */
97 #define SCCR 0x280 /* System Clock Control Register */
98 #define PLPRCR 0x284 /* PLL, Low power & Reset Control Register */
103 #define PADIR 0x950 /* Port A - Pin direction */
104 #define PAPAR 0x952 /* Port A - Pin assignment */
105 #define PAODR 0x954 /* Port A - Open Drain Control */
106 #define PADAT 0x956 /* Port A - Data */
110 #include <cyg/infra/cyg_type.h>
112 /*****************************************************************
113 Communications Processor Buffer Descriptor
114 *****************************************************************/
116 volatile unsigned short ctrl; /* status/control register */
117 volatile unsigned short length; /* buffer length */
118 volatile char *buffer; /* buffer pointer */
121 /*****************************************************************
123 *****************************************************************/
129 unsigned short rbase; /* RX BD base address */
130 unsigned short tbase; /* TX BD base address */
131 unsigned char rfcr; /* Rx function code */
132 unsigned char tfcr; /* Tx function code */
133 unsigned short mrblr; /* Rx buffer length */
134 unsigned long rstate; /* Rx internal state */
135 unsigned long rptr; /* Rx internal data pointer */
136 unsigned short rbptr; /* rb BD Pointer */
137 unsigned short rcount; /* Rx internal byte count */
138 unsigned long rtemp; /* Rx temp */
139 unsigned long tstate; /* Tx internal state */
140 unsigned long tptr; /* Tx internal data pointer */
141 unsigned short tbptr; /* Tx BD pointer */
142 unsigned short tcount; /* Tx byte count */
143 unsigned long ttemp; /* Tx temp */
144 unsigned long rcrc; /* temp receive CRC */
145 unsigned long tcrc; /* temp transmit CRC */
148 * HDLC specific parameter RAM
150 unsigned char RSRVD1[4];
151 unsigned long c_mask; /* CRC constant */
152 unsigned long c_pres; /* CRC preset */
153 unsigned short disfc; /* discarded frame counter */
154 unsigned short crcec; /* CRC error counter */
155 unsigned short abtsc; /* abort sequence counter */
156 unsigned short nmarc; /* nonmatching address rx cnt */
157 unsigned short retrc; /* frame retransmission cnt */
158 unsigned short mflr; /* maximum frame length reg */
159 unsigned short max_cnt; /* maximum length counter */
160 unsigned short rfthr; /* received frames threshold */
161 unsigned short rfcnt; /* received frames count */
162 unsigned short hmask; /* user defined frm addr mask */
163 unsigned short haddr1; /* user defined frm address 1 */
164 unsigned short haddr2; /* user defined frm address 2 */
165 unsigned short haddr3; /* user defined frm address 3 */
166 unsigned short haddr4; /* user defined frm address 4 */
167 unsigned short tmp; /* temp */
168 unsigned short tmp_mb; /* temp */
172 /*****************************************************************
173 ASYNC HDLC parameter RAM
174 *****************************************************************/
176 struct async_hdlc_pram {
180 unsigned short rbase; /* RX BD base address */
181 unsigned short tbase; /* TX BD base address */
182 unsigned char rfcr; /* Rx function code */
183 unsigned char tfcr; /* Tx function code */
184 unsigned short mrblr; /* Rx buffer length */
185 unsigned long rstate; /* Rx internal state */
186 unsigned long rptr; /* Rx internal data pointer */
187 unsigned short rbptr; /* rb BD Pointer */
188 unsigned short rcount; /* Rx internal byte count */
189 unsigned long rtemp; /* Rx temp */
190 unsigned long tstate; /* Tx internal state */
191 unsigned long tptr; /* Tx internal data pointer */
192 unsigned short tbptr; /* Tx BD pointer */
193 unsigned short tcount; /* Tx byte count */
194 unsigned long ttemp; /* Tx temp */
195 unsigned long rcrc; /* temp receive CRC */
196 unsigned long tcrc; /* temp transmit CRC */
199 * ASYNC HDLC specific parameter RAM
201 unsigned char RSRVD1[4];
202 unsigned long c_mask; /* CRC constant */
203 unsigned long c_pres; /* CRC preset */
204 unsigned short bof; /* begining of flag character */
205 unsigned short eof; /* end of flag character */
206 unsigned short esc; /* control escape character */
207 unsigned char RSRVD2[4];
208 unsigned short zero; /* zero */
209 unsigned char RSRVD3[2];
210 unsigned short rfthr; /* received frames threshold */
211 unsigned char RSRVD4[4];
212 unsigned long txctl_tbl; /* Tx ctl char mapping table */
213 unsigned long rxctl_tbl; /* Rx ctl char mapping table */
214 unsigned short nof; /* Number of opening flags */
218 /*****************************************************************
220 *****************************************************************/
223 * bits in uart control characters table
225 #define CC_INVALID 0x8000 /* control character is valid */
226 #define CC_REJ 0x4000 /* don't store char in buffer */
227 #define CC_CHAR 0x00ff /* control character */
234 unsigned short rbase; /* RX BD base address */
235 unsigned short tbase; /* TX BD base address */
236 unsigned char rfcr; /* Rx function code */
237 unsigned char tfcr; /* Tx function code */
238 unsigned short mrblr; /* Rx buffer length */
239 unsigned long rstate; /* Rx internal state */
240 unsigned long rptr; /* Rx internal data pointer */
241 unsigned short rbptr; /* rb BD Pointer */
242 unsigned short rcount; /* Rx internal byte count */
243 unsigned long rx_temp; /* Rx temp */
244 unsigned long tstate; /* Tx internal state */
245 unsigned long tptr; /* Tx internal data pointer */
246 unsigned short tbptr; /* Tx BD pointer */
247 unsigned short tcount; /* Tx byte count */
248 unsigned long ttemp; /* Tx temp */
249 unsigned long rcrc; /* temp receive CRC */
250 unsigned long tcrc; /* temp transmit CRC */
253 * UART specific parameter RAM
255 unsigned char RSRVD1[8];
256 unsigned short max_idl; /* maximum idle characters */
257 unsigned short idlc; /* rx idle counter (internal) */
258 unsigned short brkcr; /* break count register */
260 unsigned short parec; /* Rx parity error counter */
261 unsigned short frmer; /* Rx framing error counter */
262 unsigned short nosec; /* Rx noise counter */
263 unsigned short brkec; /* Rx break character counter */
264 unsigned short brkln; /* Reaceive break length */
266 unsigned short uaddr1; /* address character 1 */
267 unsigned short uaddr2; /* address character 2 */
268 unsigned short rtemp; /* temp storage */
269 unsigned short toseq; /* Tx out of sequence char */
270 unsigned short cc[8]; /* Rx control characters */
271 unsigned short rccm; /* Rx control char mask */
272 unsigned short rccr; /* Rx control char register */
273 unsigned short rlbc; /* Receive last break char */
278 /*****************************************************************
280 *****************************************************************/
286 unsigned short rbase; /* RX BD base address */
287 unsigned short tbase; /* TX BD base address */
288 unsigned char rfcr; /* Rx function code */
289 unsigned char tfcr; /* Tx function code */
290 unsigned short mrblr; /* Rx buffer length */
291 unsigned long rstate; /* Rx internal state */
292 unsigned long rptr; /* Rx internal data pointer */
293 unsigned short rbptr; /* rb BD Pointer */
294 unsigned short rcount; /* Rx internal byte count */
295 unsigned long rtemp; /* Rx temp */
296 unsigned long tstate; /* Tx internal state */
297 unsigned long tptr; /* Tx internal data pointer */
298 unsigned short tbptr; /* Tx BD pointer */
299 unsigned short tcount; /* Tx byte count */
300 unsigned long ttemp; /* Tx temp */
301 unsigned long rcrc; /* temp receive CRC */
302 unsigned long tcrc; /* temp transmit CRC */
305 * BISYNC specific parameter RAM
307 unsigned char RSRVD1[4];
308 unsigned long crcc; /* CRC Constant Temp Value */
309 unsigned short prcrc; /* Preset Receiver CRC-16/LRC */
310 unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */
311 unsigned short parec; /* Receive Parity Error Counter */
312 unsigned short bsync; /* BISYNC SYNC Character */
313 unsigned short bdle; /* BISYNC DLE Character */
314 unsigned short cc[8]; /* Rx control characters */
315 unsigned short rccm; /* Receive Control Character Mask */
318 /*****************************************************************
320 (overlaid on tx bd[5] of SCC channel[2])
321 *****************************************************************/
323 unsigned short ci_data; /* ci data */
324 unsigned short monitor_data; /* monitor data */
325 unsigned short tstate; /* transmitter state */
326 unsigned short rstate; /* receiver state */
329 /*****************************************************************
330 SPI/SMC parameter RAM
331 (overlaid on tx bd[6,7] of SCC channel[2])
332 *****************************************************************/
334 #define SPI_R 0x8000 /* Ready bit in BD */
337 unsigned short rbase; /* Rx BD Base Address */
338 unsigned short tbase; /* Tx BD Base Address */
339 unsigned char rfcr; /* Rx function code */
340 unsigned char tfcr; /* Tx function code */
341 unsigned short mrblr; /* Rx buffer length */
342 unsigned long rstate; /* Rx internal state */
343 unsigned long rptr; /* Rx internal data pointer */
344 unsigned short rbptr; /* rb BD Pointer */
345 unsigned short rcount; /* Rx internal byte count */
346 unsigned long rtemp; /* Rx temp */
347 unsigned long tstate; /* Tx internal state */
348 unsigned long tptr; /* Tx internal data pointer */
349 unsigned short tbptr; /* Tx BD pointer */
350 unsigned short tcount; /* Tx byte count */
351 unsigned long ttemp[2]; /* Tx temp */
352 unsigned short rpbase; /* Relocated param block pointer */
353 unsigned short res; /* unused */
356 struct smc_uart_pram {
357 unsigned short rbase; /* Rx BD Base Address */
358 unsigned short tbase; /* Tx BD Base Address */
359 unsigned char rfcr; /* Rx function code */
360 unsigned char tfcr; /* Tx function code */
361 unsigned short mrblr; /* Rx buffer length */
362 unsigned long rstate; /* Rx internal state */
363 unsigned long rptr; /* Rx internal data pointer */
364 unsigned short rbptr; /* rb BD Pointer */
365 unsigned short rcount; /* Rx internal byte count */
366 unsigned long rtemp; /* Rx temp */
367 unsigned long tstate; /* Tx internal state */
368 unsigned long tptr; /* Tx internal data pointer */
369 unsigned short tbptr; /* Tx BD pointer */
370 unsigned short tcount; /* Tx byte count */
371 unsigned long ttemp; /* Tx temp */
372 unsigned short max_idl; /* Maximum IDLE Characters */
373 unsigned short idlc; /* Temporary IDLE Counter */
374 unsigned short brkln; /* Last Rx Break Length */
375 unsigned short brkec; /* Rx Break Condition Counter */
376 unsigned short brkcr; /* Break Count Register (Tx) */
377 unsigned short r_mask; /* Temporary bit mask */
380 struct smc_trnsp_pram {
381 unsigned short rbase; /* Rx BD Base Address */
382 unsigned short tbase; /* Tx BD Base Address */
383 unsigned char rfcr; /* Rx function code */
384 unsigned char tfcr; /* Tx function code */
385 unsigned short mrblr; /* Rx buffer length */
386 unsigned long rstate; /* Rx internal state */
387 unsigned long rptr; /* Rx internal data pointer */
388 unsigned short rbptr; /* rb BD Pointer */
389 unsigned short rcount; /* Rx internal byte count */
390 unsigned long rtemp; /* Rx temp */
391 unsigned long tstate; /* Tx internal state */
392 unsigned long tptr; /* Tx internal data pointer */
393 unsigned short tbptr; /* Tx BD pointer */
394 unsigned short tcount; /* Tx byte count */
395 unsigned long ttemp; /* Tx temp */
396 unsigned short RSRVD[5]; /* RSRVD */
399 struct centronics_pram {
400 unsigned short rbase; /* Rx BD Base Address */
401 unsigned short tbase; /* Tx BD Base Address */
402 unsigned char fcr; /* function code */
403 unsigned char smask; /* Status Mask */
404 unsigned short mrblr; /* Rx buffer length */
405 unsigned long rstate; /* Rx internal state */
406 unsigned long rptr; /* Rx internal data pointer */
407 unsigned short rbptr; /* rb BD Pointer */
408 unsigned short rcount; /* Rx internal byte count */
409 unsigned long rtemp; /* Rx temp */
410 unsigned long tstate; /* Tx internal state */
411 unsigned long tptr; /* Tx internal data pointer */
412 unsigned short tbptr; /* Tx BD pointer */
413 unsigned short tcount; /* Tx byte count */
414 unsigned long ttemp; /* Tx temp */
415 unsigned short max_sl; /* Maximum Silence period */
416 unsigned short sl_cnt; /* Silence Counter */
417 unsigned short char1; /* CONTROL char 1 */
418 unsigned short char2; /* CONTROL char 2 */
419 unsigned short char3; /* CONTROL char 3 */
420 unsigned short char4; /* CONTROL char 4 */
421 unsigned short char5; /* CONTROL char 5 */
422 unsigned short char6; /* CONTROL char 6 */
423 unsigned short char7; /* CONTROL char 7 */
424 unsigned short char8; /* CONTROL char 8 */
425 unsigned short rccm; /* Rx Control Char Mask */
426 unsigned short rccr; /* Rx Char Control Register */
430 unsigned short ibase; /* IDMA BD Base Address */
431 unsigned short ibptr; /* IDMA buffer descriptor pointer */
432 unsigned long istate; /* IDMA internal state */
433 unsigned long itemp; /* IDMA temp */
436 struct ethernet_pram {
440 unsigned short rbase; /* RX BD base address */
441 unsigned short tbase; /* TX BD base address */
442 unsigned char rfcr; /* Rx function code */
443 unsigned char tfcr; /* Tx function code */
444 unsigned short mrblr; /* Rx buffer length */
445 unsigned long rstate; /* Rx internal state */
446 unsigned long rptr; /* Rx internal data pointer */
447 unsigned short rbptr; /* rb BD Pointer */
448 unsigned short rcount; /* Rx internal byte count */
449 unsigned long rtemp; /* Rx temp */
450 unsigned long tstate; /* Tx internal state */
451 unsigned long tptr; /* Tx internal data pointer */
452 unsigned short tbptr; /* Tx BD pointer */
453 unsigned short tcount; /* Tx byte count */
454 unsigned long ttemp; /* Tx temp */
455 unsigned long rcrc; /* temp receive CRC */
456 unsigned long tcrc; /* temp transmit CRC */
459 * ETHERNET specific parameter RAM
461 unsigned long c_pres; /* preset CRC */
462 unsigned long c_mask; /* constant mask for CRC */
463 unsigned long crcec; /* CRC error counter */
464 unsigned long alec; /* alighnment error counter */
465 unsigned long disfc; /* discard frame counter */
466 unsigned short pads; /* short frame PAD characters */
467 unsigned short ret_lim; /* retry limit threshold */
468 unsigned short ret_cnt; /* retry limit counter */
469 unsigned short mflr; /* maximum frame length reg */
470 unsigned short minflr; /* minimum frame length reg */
471 unsigned short maxd1; /* maximum DMA1 length reg */
472 unsigned short maxd2; /* maximum DMA2 length reg */
473 unsigned short maxd; /* rx max DMA */
474 unsigned short dma_cnt; /* rx dma counter */
475 unsigned short max_b; /* max bd byte count */
476 unsigned short gaddr1; /* group address filter 1 */
477 unsigned short gaddr2; /* group address filter 2 */
478 unsigned short gaddr3; /* group address filter 3 */
479 unsigned short gaddr4; /* group address filter 4 */
480 unsigned long tbuf0_data0; /* save area 0 - current frm */
481 unsigned long tbuf0_data1; /* save area 1 - current frm */
482 unsigned long tbuf0_rba0;
483 unsigned long tbuf0_crc;
484 unsigned short tbuf0_bcnt;
485 unsigned short paddr_h; /* physical address (MSB) */
486 unsigned short paddr_m; /* physical address */
487 unsigned short paddr_l; /* physical address (LSB) */
488 unsigned short p_per; /* persistence */
489 unsigned short rfbd_ptr; /* rx first bd pointer */
490 unsigned short tfbd_ptr; /* tx first bd pointer */
491 unsigned short tlbd_ptr; /* tx last bd pointer */
492 unsigned long tbuf1_data0; /* save area 0 - next frame */
493 unsigned long tbuf1_data1; /* save area 1 - next frame */
494 unsigned long tbuf1_rba0;
495 unsigned long tbuf1_crc;
496 unsigned short tbuf1_bcnt;
497 unsigned short tx_len; /* tx frame length counter */
498 unsigned short iaddr1; /* individual address filter 1*/
499 unsigned short iaddr2; /* individual address filter 2*/
500 unsigned short iaddr3; /* individual address filter 3*/
501 unsigned short iaddr4; /* individual address filter 4*/
502 unsigned short boff_cnt; /* back-off counter */
503 unsigned short taddr_h; /* temp address (MSB) */
504 unsigned short taddr_m; /* temp address */
505 unsigned short taddr_l; /* temp address (LSB) */
508 struct transparent_pram {
512 unsigned short rbase; /* RX BD base address */
513 unsigned short tbase; /* TX BD base address */
514 unsigned char rfcr; /* Rx function code */
515 unsigned char tfcr; /* Tx function code */
516 unsigned short mrblr; /* Rx buffer length */
517 unsigned long rstate; /* Rx internal state */
518 unsigned long rptr; /* Rx internal data pointer */
519 unsigned short rbptr; /* rb BD Pointer */
520 unsigned short rcount; /* Rx internal byte count */
521 unsigned long rtemp; /* Rx temp */
522 unsigned long tstate; /* Tx internal state */
523 unsigned long tptr; /* Tx internal data pointer */
524 unsigned short tbptr; /* Tx BD pointer */
525 unsigned short tcount; /* Tx byte count */
526 unsigned long ttemp; /* Tx temp */
527 unsigned long rcrc; /* temp receive CRC */
528 unsigned long tcrc; /* temp transmit CRC */
531 * TRANSPARENT specific parameter RAM
533 unsigned long crc_p; /* CRC Preset */
534 unsigned long crc_c; /* CRC constant */
539 * RISC timers parameter RAM
541 unsigned short tm_base; /* RISC timer table base adr */
542 unsigned short tm_ptr; /* RISC timer table pointer */
543 unsigned short r_tmr; /* RISC timer mode register */
544 unsigned short r_tmv; /* RISC timer valid register */
545 unsigned long tm_cmd; /* RISC timer cmd register */
546 unsigned long tm_cnt; /* RISC timer internal cnt */
551 * RISC ucode parameter RAM
553 unsigned short rev_num; /* Ucode Revision Number */
554 unsigned short d_ptr; /* MISC Dump area pointer */
555 unsigned long temp1; /* MISC Temp1 */
556 unsigned long temp2; /* MISC Temp2 */
563 unsigned short rbase; /* RX BD base address */
564 unsigned short tbase; /* TX BD base address */
565 unsigned char rfcr; /* Rx function code */
566 unsigned char tfcr; /* Tx function code */
567 unsigned short mrblr; /* Rx buffer length */
568 unsigned long rstate; /* Rx internal state */
569 unsigned long rptr; /* Rx internal data pointer */
570 unsigned short rbptr; /* rb BD Pointer */
571 unsigned short rcount; /* Rx internal byte count */
572 unsigned long rtemp; /* Rx temp */
573 unsigned long tstate; /* Tx internal state */
574 unsigned long tptr; /* Tx internal data pointer */
575 unsigned short tbptr; /* Tx BD pointer */
576 unsigned short tcount; /* Tx byte count */
577 unsigned long ttemp[2]; /* Tx temp */
578 unsigned short rpbase; /* Relocated param block pointer */
579 unsigned short res; /* unused */
583 * definitions of EPPC memory structures
585 typedef struct eppc {
586 /* BASE + 0x0000: INTERNAL REGISTERS */
589 volatile unsigned long siu_mcr; /* module configuration reg */
590 volatile unsigned long siu_sypcr; /* System protection cnt */
591 unsigned char RSRVD58[0x6];
592 volatile unsigned short siu_swsr; /* sw service */
593 volatile unsigned long siu_sipend; /* Interrupt pend reg */
594 volatile unsigned long siu_simask; /* Interrupt mask reg */
595 volatile unsigned long siu_siel; /* Interrupt edge level mask reg */
596 volatile unsigned long siu_sivec; /* Interrupt vector */
597 volatile unsigned long siu_tesr; /* Transfer error status */
598 volatile unsigned char RSRVD1[0xc];
599 volatile unsigned long dma_sdcr; /* SDMA configuration reg */
600 unsigned char RSRVD55[0x4c];
603 volatile unsigned long pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */
604 volatile unsigned long pcmcia_por0; /* PCMCIA Option Reg: Window 0 */
605 volatile unsigned long pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */
606 volatile unsigned long pcmcia_por1; /* PCMCIA Option Reg: Window 1 */
607 volatile unsigned long pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */
608 volatile unsigned long pcmcia_por2; /* PCMCIA Option Reg: Window 2 */
609 volatile unsigned long pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */
610 volatile unsigned long pcmcia_por3; /* PCMCIA Option Reg: Window 3 */
611 volatile unsigned long pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */
612 volatile unsigned long pcmcia_por4; /* PCMCIA Option Reg: Window 4 */
613 volatile unsigned long pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */
614 volatile unsigned long pcmcia_por5; /* PCMCIA Option Reg: Window 5 */
615 volatile unsigned long pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */
616 volatile unsigned long pcmcia_por6; /* PCMCIA Option Reg: Window 6 */
617 volatile unsigned long pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */
618 volatile unsigned long pcmcia_por7; /* PCMCIA Option Reg: Window 7 */
619 volatile unsigned char RSRVD2[0x20];
620 volatile unsigned long pcmcia_pgcra; /* PCMCIA Slot A Control Reg */
621 volatile unsigned long pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */
622 volatile unsigned long pcmcia_pscr; /* PCMCIA Status Reg */
623 volatile unsigned char RSRVD2a[0x4];
624 volatile unsigned long pcmcia_pipr; /* PCMCIA Pins Value Reg */
625 volatile unsigned char RSRVD2b[0x4];
626 volatile unsigned long pcmcia_per; /* PCMCIA Enable Reg */
627 volatile unsigned char RSRVD2c[0x4];
630 volatile unsigned long memc_br0; /* base register 0 */
631 volatile unsigned long memc_or0; /* option register 0 */
632 volatile unsigned long memc_br1; /* base register 1 */
633 volatile unsigned long memc_or1; /* option register 1 */
634 volatile unsigned long memc_br2; /* base register 2 */
635 volatile unsigned long memc_or2; /* option register 2 */
636 volatile unsigned long memc_br3; /* base register 3 */
637 volatile unsigned long memc_or3; /* option register 3 */
638 volatile unsigned long memc_br4; /* base register 3 */
639 volatile unsigned long memc_or4; /* option register 3 */
640 volatile unsigned long memc_br5; /* base register 3 */
641 volatile unsigned long memc_or5; /* option register 3 */
642 volatile unsigned long memc_br6; /* base register 3 */
643 volatile unsigned long memc_or6; /* option register 3 */
644 volatile unsigned long memc_br7; /* base register 3 */
645 volatile unsigned long memc_or7; /* option register 3 */
646 volatile unsigned char RSRVD3[0x24];
647 volatile unsigned long memc_mar; /* Memory address */
648 volatile unsigned long memc_mcr; /* Memory command */
649 volatile unsigned char RSRVD4[0x4];
650 volatile unsigned long memc_mamr; /* Machine A mode */
651 volatile unsigned long memc_mbmr; /* Machine B mode */
652 volatile unsigned short memc_mstat; /* Memory status */
653 volatile unsigned short memc_mptpr; /* Memory preidic timer prescalar */
654 volatile unsigned long memc_mdr; /* Memory data */
655 volatile unsigned char RSRVD5[0x80];
657 /* SYSTEM INTEGRATION TIMERS */
658 volatile unsigned short simt_tbscr; /* Time base stat&ctr */
659 volatile unsigned char RSRVD100[0x2];
660 volatile unsigned long simt_tbreff0; /* Time base reference 0 */
661 volatile unsigned long simt_tbreff1; /* Time base reference 1 */
662 volatile unsigned char RSRVD6[0x14];
663 volatile unsigned short simt_rtcsc; /* Realtime clk stat&cntr 1 */
664 volatile unsigned char RSRVD110[0x2];
665 volatile unsigned long simt_rtc; /* Realtime clock */
666 volatile unsigned long simt_rtsec; /* Realtime alarm seconds */
667 volatile unsigned long simt_rtcal; /* Realtime alarm */
668 volatile unsigned char RSRVD56[0x10];
669 volatile unsigned long simt_piscr; /* PIT stat&ctrl */
670 volatile unsigned long simt_pitc; /* PIT counter */
671 volatile unsigned long simt_pitr; /* PIT */
672 volatile unsigned char RSRVD7[0x34];
675 volatile unsigned long clkr_sccr; /* System clk cntrl */
676 volatile unsigned long clkr_plprcr; /* PLL reset&ctrl */
677 volatile unsigned long clkr_rsr; /* reset status */
678 volatile unsigned char RSRVD66a[0x74];
680 /* System Integration Timers Keys */
681 volatile unsigned long simt_tbscrk; /* Timebase Status&Ctrl Key */
682 volatile unsigned long simt_tbreff0k; /* Timebase Reference 0 Key */
683 volatile unsigned long simt_tbreff1k; /* Timebase Reference 1 Key */
684 volatile unsigned long simt_tbk; /* Timebase and Decrementer Key */
685 volatile unsigned char RSRVD66b[0x10];
686 volatile unsigned long simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */
687 volatile unsigned long simt_rtck; /* Real-Time Clock Key */
688 volatile unsigned long simt_rtseck; /* Real-Time Alarm Seconds Key */
689 volatile unsigned long simt_rtcalk; /* Real-Time Alarm Key */
690 volatile unsigned char RSRVD66c[0x10];
691 volatile unsigned long simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */
692 volatile unsigned long simt_pitck; /* Periodic Interrupt Count Key */
693 volatile unsigned char RSRVD66d[0x38];
696 /* Clock and Reset Keys */
697 volatile unsigned long clkr_sccrk; /* System Clock Control Key */
698 volatile unsigned long clkr_plprcrk; /* PLL, Low Power and Reset Control Key */
699 volatile unsigned long clkr_rsrk; /* Reset Status Key */
700 volatile unsigned char RSRVD66e[0x4b4];
702 volatile unsigned long lcd_lccr; /* configuration Reg */
703 volatile unsigned long lcd_lchcr; /* Horizontal ctl Reg */
704 volatile unsigned long lcd_lcvcr; /* Vertical ctl Reg */
705 unsigned char RSRVD67[4];
706 volatile unsigned long lcd_lcfaa; /* Frame buffer A Address */
707 volatile unsigned long lcd_lcfba; /* Frame buffer B Address */
708 volatile unsigned char lcd_lcsr; /* Status Reg */
709 volatile unsigned char RSRVD9[0x7];
712 volatile unsigned char i2c_i2mod; /* i2c mode */
713 unsigned char RSRVD59[3];
714 volatile unsigned char i2c_i2add; /* i2c address */
715 unsigned char RSRVD60[3];
716 volatile unsigned char i2c_i2brg; /* i2c brg */
717 unsigned char RSRVD61[3];
718 volatile unsigned char i2c_i2com; /* i2c command */
719 unsigned char RSRVD62[3];
720 volatile unsigned char i2c_i2cer; /* i2c event */
721 unsigned char RSRVD63[3];
722 volatile unsigned char i2c_i2cmr; /* i2c mask */
723 volatile unsigned char RSRVD10[0x0b];
724 volatile unsigned char i2c_spare_pram[0x80]; /* Used by patched ucode */
727 volatile unsigned char RSRVD11[0x4];
728 volatile unsigned long dma_sdar; /* SDMA address reg */
729 volatile unsigned char dma_sdsr; /* SDMA status reg */
730 volatile unsigned char RSRVD12[0x3];
731 volatile unsigned char dma_sdmr; /* SDMA mask reg */
732 volatile unsigned char RSRVD13[0x3];
733 volatile unsigned char dma_idsr1; /* IDMA1 status reg */
734 volatile unsigned char RSRVD14[0x3];
735 volatile unsigned char dma_idmr1; /* IDMA1 mask reg */
736 volatile unsigned char RSRVD15[0x3];
737 volatile unsigned char dma_idsr2; /* IDMA2 status reg */
738 volatile unsigned char RSRVD16[0x3];
739 volatile unsigned char dma_idmr2; /* IDMA2 mask reg */
740 volatile unsigned char RSRVD17[0x13];
742 /* CPM Interrupt Controller */
743 volatile unsigned short cpmi_civr; /* CP interrupt vector reg */
744 volatile unsigned char RSRVD19[0xe];
745 volatile unsigned long cpmi_cicr; /* CP interrupt configuration reg */
746 volatile unsigned long cpmi_cipr; /* CP interrupt pending reg */
747 volatile unsigned long cpmi_cimr; /* CP interrupt mask reg */
748 volatile unsigned long cpmi_cisr; /* CP interrupt in-service reg */
751 volatile unsigned short pio_padir; /* port A data direction reg */
752 volatile unsigned short pio_papar; /* port A pin assignment reg */
753 volatile unsigned short pio_paodr; /* port A open drain reg */
754 volatile unsigned short pio_padat; /* port A data register */
755 volatile unsigned char RSRVD20[0x8];
756 volatile unsigned short pio_pcdir; /* port C data direction reg */
757 volatile unsigned short pio_pcpar; /* port C pin assignment reg */
758 volatile unsigned short pio_pcso; /* port C special options */
759 volatile unsigned short pio_pcdat; /* port C data register */
760 volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
761 unsigned char RSRVD64[6];
762 volatile unsigned short pio_pddir; /* port D Data Direction reg */
763 volatile unsigned short pio_pdpar; /* port D pin assignment reg */
764 unsigned char RSRVD65[2];
765 volatile unsigned short pio_pddat; /* port D data reg */
766 volatile unsigned char RSRVD21[0x8];
769 volatile unsigned short timer_tgcr; /* timer global configuration reg */
770 volatile unsigned char RSRVD22[0xe];
771 volatile unsigned short timer_tmr1; /* timer 1 mode reg */
772 volatile unsigned short timer_tmr2; /* timer 2 mode reg */
773 volatile unsigned short timer_trr1; /* timer 1 referance reg */
774 volatile unsigned short timer_trr2; /* timer 2 referance reg */
775 volatile unsigned short timer_tcr1; /* timer 1 capture reg */
776 volatile unsigned short timer_tcr2; /* timer 2 capture reg */
777 volatile unsigned short timer_tcn1; /* timer 1 counter reg */
778 volatile unsigned short timer_tcn2; /* timer 2 counter reg */
779 volatile unsigned short timer_tmr3; /* timer 3 mode reg */
780 volatile unsigned short timer_tmr4; /* timer 4 mode reg */
781 volatile unsigned short timer_trr3; /* timer 3 referance reg */
782 volatile unsigned short timer_trr4; /* timer 4 referance reg */
783 volatile unsigned short timer_tcr3; /* timer 3 capture reg */
784 volatile unsigned short timer_tcr4; /* timer 4 capture reg */
785 volatile unsigned short timer_tcn3; /* timer 3 counter reg */
786 volatile unsigned short timer_tcn4; /* timer 4 counter reg */
787 volatile unsigned short timer_ter1; /* timer 1 event reg */
788 volatile unsigned short timer_ter2; /* timer 2 event reg */
789 volatile unsigned short timer_ter3; /* timer 3 event reg */
790 volatile unsigned short timer_ter4; /* timer 4 event reg */
791 volatile unsigned char RSRVD23[0x8];
794 volatile unsigned short cp_cr; /* command register */
795 volatile unsigned char RSRVD24[0x2];
796 volatile unsigned short cp_rccr; /* main configuration reg */
797 volatile unsigned char RSRVD25;
798 volatile unsigned char cp_resv1; /* RSRVD reg */
799 volatile unsigned long cp_resv2; /* RSRVD reg */
800 volatile unsigned short cp_rctr1; /* ram break register 1 */
801 volatile unsigned short cp_rctr2; /* ram break register 2 */
802 volatile unsigned short cp_rctr3; /* ram break register 3 */
803 volatile unsigned short cp_rctr4; /* ram break register 4 */
804 volatile unsigned char RSRVD26[0x2];
805 volatile unsigned short cp_rter; /* RISC timers event reg */
806 volatile unsigned char RSRVD27[0x2];
807 volatile unsigned short cp_rtmr; /* RISC timers mask reg */
808 volatile unsigned char RSRVD28[0x14];
811 volatile unsigned long brgc1; /* BRG1 configuration reg */
812 volatile unsigned long brgc2; /* BRG2 configuration reg */
813 volatile unsigned long brgc3; /* BRG3 configuration reg */
814 volatile unsigned long brgc4; /* BRG4 configuration reg */
818 volatile unsigned long scc_gsmr_l; /* SCC Gen mode (LOW) */
819 volatile unsigned long scc_gsmr_h; /* SCC Gen mode (HIGH) */
820 volatile unsigned short scc_psmr; /* protocol specific mode register */
821 volatile unsigned char RSRVD29[0x2];
822 volatile unsigned short scc_todr; /* SCC transmit on demand */
823 volatile unsigned short scc_dsr; /* SCC data sync reg */
824 volatile unsigned short scc_scce; /* SCC event reg */
825 volatile unsigned char RSRVD30[0x2];
826 volatile unsigned short scc_sccm; /* SCC mask reg */
827 volatile unsigned char RSRVD31[0x1];
828 volatile unsigned char scc_sccs; /* SCC status reg */
829 volatile unsigned char RSRVD32[0x8];
834 volatile unsigned char RSRVD34[0x2];
835 volatile unsigned short smc_smcmr; /* SMC mode reg */
836 volatile unsigned char RSRVD35[0x2];
837 volatile unsigned char smc_smce; /* SMC event reg */
838 volatile unsigned char RSRVD36[0x3];
839 volatile unsigned char smc_smcm; /* SMC mask reg */
840 volatile unsigned char RSRVD37[0x5];
844 volatile unsigned short spi_spmode; /* SPI mode reg */
845 volatile unsigned char RSRVD38[0x4];
846 volatile unsigned char spi_spie; /* SPI event reg */
847 volatile unsigned char RSRVD39[0x3];
848 volatile unsigned char spi_spim; /* SPI mask reg */
849 volatile unsigned char RSRVD40[0x2];
850 volatile unsigned char spi_spcom; /* SPI command reg */
851 volatile unsigned char RSRVD41[0x4];
854 volatile unsigned short pip_pipc; /* pip configuration reg */
855 volatile unsigned char RSRVD42[0x2];
856 volatile unsigned short pip_ptpr; /* pip timing parameters reg */
857 volatile unsigned long pip_pbdir; /* port b data direction reg */
858 volatile unsigned long pip_pbpar; /* port b pin assignment reg */
859 volatile unsigned char RSRVD43[0x2];
860 volatile unsigned short pip_pbodr; /* port b open drain reg */
861 volatile unsigned long pip_pbdat; /* port b data reg */
862 volatile unsigned char RSRVD44[0x18];
864 /* Serial Interface */
865 volatile unsigned long si_simode; /* SI mode register */
866 volatile unsigned char si_sigmr; /* SI global mode register */
867 volatile unsigned char RSRVD45;
868 volatile unsigned char si_sistr; /* SI status register */
869 volatile unsigned char si_sicmr; /* SI command register */
870 volatile unsigned char RSRVD46[0x4];
871 volatile unsigned long si_sicr; /* SI clock routing */
872 volatile unsigned long si_sirp; /* SI ram pointers */
873 volatile unsigned char RSRVD47[0x10c];
874 volatile unsigned char si_siram[0x200];/* SI routing ram */
875 volatile unsigned short lcd_lcolr[256]; /* LCD Color RAM -- REV A.x */
876 volatile unsigned char RSRVD48[0x1000];
878 /* BASE + 0x2000: user data memory */
879 volatile unsigned char udata_ucode[0x800]; /* user data bd's Ucode*/
880 volatile unsigned char bd[0x700]; /* buffer descriptors, data */
881 volatile unsigned char udata_ext[0x100]; /* extension area for downloaded ucode */
882 volatile unsigned char RSRVD49[0x0C00];
884 /* BASE + 0x3c00: PARAMETER RAM */
890 struct bisync_pram b;
891 struct transparent_pram t;
892 struct async_hdlc_pram a;
893 unsigned char RSRVD50[0x80];
894 } pscc; /* scc parameter area (protocol dependent) */
899 unsigned char RSRVD56[0x10];
900 struct idma_pram idma1;
904 struct timer_pram timer;
905 struct idma_pram idma2;
909 struct smc_uart_pram u;
910 struct smc_trnsp_pram t;
911 struct centronics_pram c;
913 unsigned char modem_param[0x40];
916 unsigned char RSRVD54[0x40];
917 struct ucode_pram ucode;
921 struct ethernet_pram enet_scc;
922 unsigned char pr[0x100];
927 static inline EPPC *eppc_base(void)
933 "andis. %0,%0,65535 \n\t"
940 // Function used to reset [only once!] the CPM
941 __externC void _mpc8xx_reset_cpm(void);
943 // Function used to allocate space in shared memory area
944 // typically used for buffer descriptors, etc.
945 __externC unsigned short _mpc8xx_allocBd(int len);
947 // Function used to manage the pool of baud rate generators
948 __externC unsigned long *_mpc8xx_allocate_brg(int port);
950 #define QUICC_BD_BASE 0x2000 // Start of shared memory
951 #define QUICC_BD_END 0x3000 // End of shared memory
954 #endif /* __ASSEMBLER__ */
956 /* Memory Periodic Timer Prescaler Register values */
957 #define PTP_DIV2 0x2000
958 #define PTP_DIV4 0x1000
959 #define PTP_DIV8 0x0800
960 #define PTP_DIV16 0x0400
961 #define PTP_DIV32 0x0200
962 #define PTP_DIV64 0x0100
964 // Command Processor Module (CPM)
966 // Buffer descriptor control bits
967 #define QUICC_BD_CTL_Ready 0x8000 // Buffer contains data (tx) or is empty (rx)
968 #define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in list
969 #define QUICC_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx)
970 #define QUICC_BD_CTL_Last 0x0800 // Last buffer in a sequence
971 #define QUICC_BD_CTL_Frame 0x0010 // Framing Error
972 #define QUICC_BD_CTL_Parity 0x0008 // Parity Error
973 #define QUICC_BD_CTL_MASK 0xB000 // User settable bits
976 #define QUICC_CPM_CR_INIT_TXRX 0x0000 // Initialize both Tx and Rx chains
977 #define QUICC_CPM_CR_INIT_RX 0x0100 // Initialize Rx chains
978 #define QUICC_CPM_CR_INIT_TX 0x0200 // Initialize Tx chains
979 #define QUICC_CPM_CR_HUNT_MODE 0x0300 // Start "hunt" mode
980 #define QUICC_CPM_CR_STOP_TX 0x0400 // Stop transmitter
981 #define QUICC_CPM_CR_RESTART_TX 0x0600 // Restart transmitter
982 #define QUICC_CPM_CR_RESET 0x8000 // Reset CPM
983 #define QUICC_CPM_CR_BUSY 0x0001 // Kick CPM - busy indicator
986 #define QUICC_CPM_SCC1 0x0000
987 #define QUICC_CPM_I2C 0x0010
988 #define QUICC_CPM_SCC2 0x0040
989 #define QUICC_CPM_SCC3 0x0080
990 #define QUICC_CPM_SMC1 0x0090
991 #define QUICC_CPM_SCC4 0x00C0
992 #define QUICC_CPM_SMC2 0x00D0
994 // SMC Events (interrupts)
995 #define QUICC_SMCE_BRK 0x10 // Break received
996 #define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
997 #define QUICC_SMCE_TX 0x02 // Tx interrupt
998 #define QUICC_SMCE_RX 0x01 // Rx interrupt
1000 // SMC Mode Register
1001 #define QUICC_SMCMR_CLEN(n) (n<<11) // Character length + parity + stop bits
1002 #define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2)
1003 #define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable)
1004 #define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even)
1005 #define QUICC_SMCMR_UART (2<<4) // UART mode
1006 #define QUICC_SMCMR_TEN (1<<1) // Enable transmitter
1007 #define QUICC_SMCMR_REN (1<<0) // Enable receiver
1010 #define QUICC_SMC_CMD_InitTxRx (0<<8)
1011 #define QUICC_SMC_CMD_InitTx (1<<8)
1012 #define QUICC_SMC_CMD_InitRx (2<<8)
1013 #define QUICC_SMC_CMD_StopTx (4<<8)
1014 #define QUICC_SMC_CMD_RestartTx (6<<8)
1015 #define QUICC_SMC_CMD_Reset 0x8000
1016 #define QUICC_SMC_CMD_Go 0x0001
1018 // SCC PSMR masks ....
1019 #define QUICC_SCC_PSMR_ASYNC 0x8000
1020 #define QUICC_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb)
1021 #define QUICC_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8)
1022 #define QUICC_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled)
1023 #define QUICC_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high)
1024 #define QUICC_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high)
1027 #define QUICC_SCC_DSR_FULL 0x7e7e
1028 #define QUICC_SCC_DSR_HALF 0x467e
1030 // SCC GSMR masks ...
1031 #define QUICC_SCC_GSMR_H_INIT 0x00000060
1032 #define QUICC_SCC_GSMR_L_INIT 0x00028004
1033 #define QUICC_SCC_GSMR_L_Tx 0x00000010
1034 #define QUICC_SCC_GSMR_L_Rx 0x00000020
1036 // SCC Events (interrupts)
1037 #define QUICC_SCCE_BRK 0x0040
1038 #define QUICC_SCCE_BSY 0x0004
1039 #define QUICC_SCCE_TX 0x0002
1040 #define QUICC_SCCE_RX 0x0001
1042 #endif // ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H