# CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
# --> 399
# Legal values: 266 399
+
+ # The following properties are affected by this value
+ # option CYGOPT_MX27_WORKAROUND_ENGcm11563
+ # Requires: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"
};
# System clock (hclk) rate
# Default value: ""
};
+# Enable workaround for Erratum ENGcm11563
+# This option enables the software workaround for
+# ENGcm11563 (ARM core lockup due to invalid
+# duty cycle of ARM clock at 399 MHz.
+#
+cdl_option CYGOPT_MX27_WORKAROUND_ENGcm11563 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 399
+ # --> 1
+};
+
# <
# Memory layout
#
# CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT (unknown) == 0
# --> 399
# Legal values: 266 399
+
+ # The following properties are affected by this value
+ # option CYGOPT_MX27_WORKAROUND_ENGcm11563
+ # Requires: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"
};
# System clock (hclk) rate
# Default value: ""
};
+# Enable workaround for Erratum ENGcm11563
+# This option enables the software workaround for
+# ENGcm11563 (ARM core lockup due to invalid
+# duty cycle of ARM clock at 399 MHz.
+#
+cdl_option CYGOPT_MX27_WORKAROUND_ENGcm11563 {
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+ # Requires: CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"
+ # CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 399
+ # --> 1
+};
+
# <
# Memory layout
#
the set of global flags if present."
}
+ cdl_option CYGOPT_MX27_WORKAROUND_ENGcm11563 {
+ display "Enable workaround for Erratum ENGcm11563"
+ flavor bool
+ default_value { 1 }
+ requires {CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == "399"}
+ description "
+ This option enables the software workaround for
+ ENGcm11563 (ARM core lockup due to invalid
+ duty cycle of ARM clock at 399 MHz."
+ }
}
cdl_component CYGHWR_MEMORY_LAYOUT {
ldr r0, SOC_CRM_BASE_W
// disable PLL update first
ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+ /* clear ARM_SRC & ARM_DIV required as workaround for ENGcm12387 */
+ bic r1, r1, #((1 << 15) | (3 << 12))
orr r1, r1, #(1 << 31)
#ifdef PLL_REF_CLK_32768HZ
- orr r1, r1, #(1 << 3) // disable OSC26M
+ orr r1, r1, #(1 << 3) // disable 26MHz osc
#else
bic r1, r1, #(1 << 3) // enable 26MHz osc
#endif
str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+#ifdef PLL_REF_CLK_32768HZ
+ // Make sure to use CKIL
+ bic r1, r1, #(3 << 16)
+#else
+ orr r1, r1, #(3 << 16) // select 26MHz
+#endif
orr r1, r1, #(0x3 << 18) // SPLL_RESTART | MPLL_RESTART
orr r1, r1, #(0x3 << 0) // SPLL_ENABLE | MPLL_ENABLE
str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]