+/***************************************************************************
+*
+* MX51_IOMUX.H
+*
+* Macros definations for MX51 IPUv3e IOMUX.
+*
+***************************************************************************
+*
+* Author(s) : Ray Sun-B17777 <Yanfei.Sun@freescale.com>
+* Create Date: 2008-11-10
+* Description : i.MX51 IOMUX defines
+*
+***************************************************************************/
+
+#ifndef _MX51_IOMUX_H_
+#define _MX51_IOMUX_H_
+
+#include <cyg/hal/hal_soc.h>
+
+#define GPR_BASE_ADDR (IOMUXC_BASE_ADDR + 0x0) // 0x0
+#define OBSRV_BASE_ADDR (GPR_BASE_ADDR + 0x8) // 0x8
+#define SW_MUX_BASE_ADDR (OBSRV_BASE_ADDR + 0x14) // 0x1c
+#define SW_PAD_BASE_ADDR (SW_MUX_BASE_ADDR + 0x3d4) // 0x3f0
+#define SW_GRP_BASE_ADDR (SW_PAD_BASE_ADDR + 0x42c) // 0x81c
+#define SW_INPUT_PORT_BASE_ADDR (SW_GRP_BASE_ADDR + 0xa8) // 0x8c4
+#define SELECT_INPUT_BASE_ADDR (SW_INPUT_PORT_BASE_ADDR + 0x0) // 0x8c4
+
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 (SW_MUX_BASE_ADDR + 0x0) // 0x1c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 (SW_MUX_BASE_ADDR + 0x4) // 0x20
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 (SW_MUX_BASE_ADDR + 0x8) // 0x24
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 (SW_MUX_BASE_ADDR + 0xc) // 0x28
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 (SW_MUX_BASE_ADDR + 0x10) // 0x2c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 (SW_MUX_BASE_ADDR + 0x14) // 0x30
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 (SW_MUX_BASE_ADDR + 0x18) // 0x34
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 (SW_MUX_BASE_ADDR + 0x1c) // 0x38
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 (SW_MUX_BASE_ADDR + 0x20) // 0x3c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 (SW_MUX_BASE_ADDR + 0x24) // 0x40
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 (SW_MUX_BASE_ADDR + 0x28) // 0x44
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 (SW_MUX_BASE_ADDR + 0x2c) // 0x48
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 (SW_MUX_BASE_ADDR + 0x30) // 0x4c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 (SW_MUX_BASE_ADDR + 0x34) // 0x50
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 (SW_MUX_BASE_ADDR + 0x38) // 0x54
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 (SW_MUX_BASE_ADDR + 0x3c) // 0x58
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D16 (SW_MUX_BASE_ADDR + 0x40) // 0x5c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D17 (SW_MUX_BASE_ADDR + 0x44) // 0x60
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D18 (SW_MUX_BASE_ADDR + 0x48) // 0x64
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D19 (SW_MUX_BASE_ADDR + 0x4c) // 0x68
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D20 (SW_MUX_BASE_ADDR + 0x50) // 0x6c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D21 (SW_MUX_BASE_ADDR + 0x54) // 0x70
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D22 (SW_MUX_BASE_ADDR + 0x58) // 0x74
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D23 (SW_MUX_BASE_ADDR + 0x5c) // 0x78
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D24 (SW_MUX_BASE_ADDR + 0x60) // 0x7c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D25 (SW_MUX_BASE_ADDR + 0x64) // 0x80
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D26 (SW_MUX_BASE_ADDR + 0x68) // 0x84
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D27 (SW_MUX_BASE_ADDR + 0x6c) // 0x88
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D28 (SW_MUX_BASE_ADDR + 0x70) // 0x8c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D29 (SW_MUX_BASE_ADDR + 0x74) // 0x90
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D30 (SW_MUX_BASE_ADDR + 0x78) // 0x94
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D31 (SW_MUX_BASE_ADDR + 0x7c) // 0x98
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A16 (SW_MUX_BASE_ADDR + 0x80) // 0x9c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A17 (SW_MUX_BASE_ADDR + 0x84) // 0xa0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A18 (SW_MUX_BASE_ADDR + 0x88) // 0xa4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A19 (SW_MUX_BASE_ADDR + 0x8c) // 0xa8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A20 (SW_MUX_BASE_ADDR + 0x90) // 0xac
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A21 (SW_MUX_BASE_ADDR + 0x94) // 0xb0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A22 (SW_MUX_BASE_ADDR + 0x98) // 0xb4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A23 (SW_MUX_BASE_ADDR + 0x9c) // 0xb8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A24 (SW_MUX_BASE_ADDR + 0xa0) // 0xbc
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A25 (SW_MUX_BASE_ADDR + 0xa4) // 0xc0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A26 (SW_MUX_BASE_ADDR + 0xa8) // 0xc4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A27 (SW_MUX_BASE_ADDR + 0xac) // 0xc8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 (SW_MUX_BASE_ADDR + 0xb0) // 0xcc
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 (SW_MUX_BASE_ADDR + 0xb4) // 0xd0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 (SW_MUX_BASE_ADDR + 0xb8) // 0xd4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 (SW_MUX_BASE_ADDR + 0xbc) // 0xd8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE (SW_MUX_BASE_ADDR + 0xc0) // 0xdc
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 (SW_MUX_BASE_ADDR + 0xc4) // 0xe0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 (SW_MUX_BASE_ADDR + 0xc8) // 0xe4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2 (SW_MUX_BASE_ADDR + 0xcc) // 0xe8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS3 (SW_MUX_BASE_ADDR + 0xd0) // 0xec
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS4 (SW_MUX_BASE_ADDR + 0xd4) // 0xf0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS5 (SW_MUX_BASE_ADDR + 0xd8) // 0xf4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK (SW_MUX_BASE_ADDR + 0xdc) // 0xf8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA (SW_MUX_BASE_ADDR + 0xe0) // 0xfc
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE (SW_MUX_BASE_ADDR + 0xe4) // 0x100
+#define IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1 (SW_MUX_BASE_ADDR + 0xe8) // 0x104
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B (SW_MUX_BASE_ADDR + 0xec) // 0x108
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B (SW_MUX_BASE_ADDR + 0xf0) // 0x10c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE (SW_MUX_BASE_ADDR + 0xf4) // 0x110
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE (SW_MUX_BASE_ADDR + 0xf8) // 0x114
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B (SW_MUX_BASE_ADDR + 0xfc) // 0x118
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 (SW_MUX_BASE_ADDR + 0x100) // 0x11c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 (SW_MUX_BASE_ADDR + 0x104) // 0x120
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 (SW_MUX_BASE_ADDR + 0x108) // 0x124
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 (SW_MUX_BASE_ADDR + 0x10c) // 0x128
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND (SW_MUX_BASE_ADDR + 0x110) // 0x12c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 (SW_MUX_BASE_ADDR + 0x114) // 0x130
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 (SW_MUX_BASE_ADDR + 0x118) // 0x134
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 (SW_MUX_BASE_ADDR + 0x11c) // 0x138
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 (SW_MUX_BASE_ADDR + 0x120) // 0x13c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 (SW_MUX_BASE_ADDR + 0x124) // 0x140
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 (SW_MUX_BASE_ADDR + 0x128) // 0x144
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 (SW_MUX_BASE_ADDR + 0x12c) // 0x148
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 (SW_MUX_BASE_ADDR + 0x130) // 0x14c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT (SW_MUX_BASE_ADDR + 0x134) // 0x150
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 (SW_MUX_BASE_ADDR + 0x138) // 0x154
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 (SW_MUX_BASE_ADDR + 0x13c) // 0x158
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 (SW_MUX_BASE_ADDR + 0x140) // 0x15c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 (SW_MUX_BASE_ADDR + 0x144) // 0x160
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 (SW_MUX_BASE_ADDR + 0x148) // 0x164
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 (SW_MUX_BASE_ADDR + 0x14c) // 0x168
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 (SW_MUX_BASE_ADDR + 0x150) // 0x16c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 (SW_MUX_BASE_ADDR + 0x154) // 0x170
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 (SW_MUX_BASE_ADDR + 0x158) // 0x174
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 (SW_MUX_BASE_ADDR + 0x15c) // 0x178
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 (SW_MUX_BASE_ADDR + 0x160) // 0x17c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 (SW_MUX_BASE_ADDR + 0x164) // 0x180
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 (SW_MUX_BASE_ADDR + 0x168) // 0x184
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 (SW_MUX_BASE_ADDR + 0x16c) // 0x188
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 (SW_MUX_BASE_ADDR + 0x170) // 0x18c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 (SW_MUX_BASE_ADDR + 0x174) // 0x190
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D8 (SW_MUX_BASE_ADDR + 0x178) // 0x194
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D9 (SW_MUX_BASE_ADDR + 0x17c) // 0x198
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D10 (SW_MUX_BASE_ADDR + 0x180) // 0x19c
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D11 (SW_MUX_BASE_ADDR + 0x184) // 0x1a0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D12 (SW_MUX_BASE_ADDR + 0x188) // 0x1a4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D13 (SW_MUX_BASE_ADDR + 0x18c) // 0x1a8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D14 (SW_MUX_BASE_ADDR + 0x190) // 0x1ac
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D15 (SW_MUX_BASE_ADDR + 0x194) // 0x1b0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D16 (SW_MUX_BASE_ADDR + 0x198) // 0x1b4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D17 (SW_MUX_BASE_ADDR + 0x19c) // 0x1b8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D18 (SW_MUX_BASE_ADDR + 0x1a0) // 0x1bc
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D19 (SW_MUX_BASE_ADDR + 0x1a4) // 0x1c0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC (SW_MUX_BASE_ADDR + 0x1a8) // 0x1c4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC (SW_MUX_BASE_ADDR + 0x1ac) // 0x1c8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D12 (SW_MUX_BASE_ADDR + 0x1b0) // 0x1cc
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D13 (SW_MUX_BASE_ADDR + 0x1b4) // 0x1d0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D14 (SW_MUX_BASE_ADDR + 0x1b8) // 0x1d4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D15 (SW_MUX_BASE_ADDR + 0x1bc) // 0x1d8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D16 (SW_MUX_BASE_ADDR + 0x1c0) // 0x1dc
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D17 (SW_MUX_BASE_ADDR + 0x1c4) // 0x1e0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D18 (SW_MUX_BASE_ADDR + 0x1c8) // 0x1e4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D19 (SW_MUX_BASE_ADDR + 0x1cc) // 0x1e8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC (SW_MUX_BASE_ADDR + 0x1d0) // 0x1ec
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC (SW_MUX_BASE_ADDR + 0x1d4) // 0x1f0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK (SW_MUX_BASE_ADDR + 0x1d8) // 0x1f4
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK (SW_MUX_BASE_ADDR + 0x1dc) // 0x1f8
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT (SW_MUX_BASE_ADDR + 0x1e0) // 0x1fc
+#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD (SW_MUX_BASE_ADDR + 0x1e4) // 0x200
+#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD (SW_MUX_BASE_ADDR + 0x1e8) // 0x204
+#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK (SW_MUX_BASE_ADDR + 0x1ec) // 0x208
+#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS (SW_MUX_BASE_ADDR + 0x1f0) // 0x20c
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI (SW_MUX_BASE_ADDR + 0x1f4) // 0x210
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO (SW_MUX_BASE_ADDR + 0x1f8) // 0x214
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0 (SW_MUX_BASE_ADDR + 0x1fc) // 0x218
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1 (SW_MUX_BASE_ADDR + 0x200) // 0x21c
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY (SW_MUX_BASE_ADDR + 0x204) // 0x220
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK (SW_MUX_BASE_ADDR + 0x208) // 0x224
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD (SW_MUX_BASE_ADDR + 0x20c) // 0x228
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD (SW_MUX_BASE_ADDR + 0x210) // 0x22c
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS (SW_MUX_BASE_ADDR + 0x214) // 0x230
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS (SW_MUX_BASE_ADDR + 0x218) // 0x234
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD (SW_MUX_BASE_ADDR + 0x21c) // 0x238
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD (SW_MUX_BASE_ADDR + 0x220) // 0x23c
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD (SW_MUX_BASE_ADDR + 0x224) // 0x240
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD (SW_MUX_BASE_ADDR + 0x228) // 0x244
+#define IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE (SW_MUX_BASE_ADDR + 0x22c) // 0x248
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 (SW_MUX_BASE_ADDR + 0x230) // 0x24c
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 (SW_MUX_BASE_ADDR + 0x234) // 0x250
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 (SW_MUX_BASE_ADDR + 0x238) // 0x254
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 (SW_MUX_BASE_ADDR + 0x23c) // 0x258
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 (SW_MUX_BASE_ADDR + 0x240) // 0x25c
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 (SW_MUX_BASE_ADDR + 0x244) // 0x260
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 (SW_MUX_BASE_ADDR + 0x248) // 0x264
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 (SW_MUX_BASE_ADDR + 0x24c) // 0x268
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 (SW_MUX_BASE_ADDR + 0x250) // 0x26c
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL5 (SW_MUX_BASE_ADDR + 0x254) // 0x270
+#define IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B (SW_MUX_BASE_ADDR + 0x258) // 0x274
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK (SW_MUX_BASE_ADDR + 0x25c) // 0x278
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR (SW_MUX_BASE_ADDR + 0x260) // 0x27c
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_STP (SW_MUX_BASE_ADDR + 0x264) // 0x280
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT (SW_MUX_BASE_ADDR + 0x268) // 0x284
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0 (SW_MUX_BASE_ADDR + 0x26c) // 0x288
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1 (SW_MUX_BASE_ADDR + 0x270) // 0x28c
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2 (SW_MUX_BASE_ADDR + 0x274) // 0x290
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3 (SW_MUX_BASE_ADDR + 0x278) // 0x294
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4 (SW_MUX_BASE_ADDR + 0x27c) // 0x298
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5 (SW_MUX_BASE_ADDR + 0x280) // 0x29c
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6 (SW_MUX_BASE_ADDR + 0x284) // 0x2a0
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7 (SW_MUX_BASE_ADDR + 0x288) // 0x2a4
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11 (SW_MUX_BASE_ADDR + 0x28c) // 0x2a8
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12 (SW_MUX_BASE_ADDR + 0x290) // 0x2ac
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13 (SW_MUX_BASE_ADDR + 0x294) // 0x2b0
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS (SW_MUX_BASE_ADDR + 0x298) // 0x2b4
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS (SW_MUX_BASE_ADDR + 0x29c) // 0x2b8
+#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN (SW_MUX_BASE_ADDR + 0x2a0) // 0x2bc
+#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO (SW_MUX_BASE_ADDR + 0x2a4) // 0x2c0
+#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK (SW_MUX_BASE_ADDR + 0x2a8) // 0x2c4
+#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS (SW_MUX_BASE_ADDR + 0x2ac) // 0x2c8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0 (SW_MUX_BASE_ADDR + 0x2b0) // 0x2cc
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1 (SW_MUX_BASE_ADDR + 0x2b4) // 0x2d0
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2 (SW_MUX_BASE_ADDR + 0x2b8) // 0x2d4
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3 (SW_MUX_BASE_ADDR + 0x2bc) // 0x2d8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4 (SW_MUX_BASE_ADDR + 0x2c0) // 0x2dc
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5 (SW_MUX_BASE_ADDR + 0x2c4) // 0x2e0
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6 (SW_MUX_BASE_ADDR + 0x2c8) // 0x2e4
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7 (SW_MUX_BASE_ADDR + 0x2cc) // 0x2e8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8 (SW_MUX_BASE_ADDR + 0x2d0) // 0x2ec
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9 (SW_MUX_BASE_ADDR + 0x2d4) // 0x2f0
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10 (SW_MUX_BASE_ADDR + 0x2d8) // 0x2f4
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11 (SW_MUX_BASE_ADDR + 0x2dc) // 0x2f8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12 (SW_MUX_BASE_ADDR + 0x2e0) // 0x2fc
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13 (SW_MUX_BASE_ADDR + 0x2e4) // 0x300
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14 (SW_MUX_BASE_ADDR + 0x2e8) // 0x304
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15 (SW_MUX_BASE_ADDR + 0x2ec) // 0x308
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16 (SW_MUX_BASE_ADDR + 0x2f0) // 0x30c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17 (SW_MUX_BASE_ADDR + 0x2f4) // 0x310
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18 (SW_MUX_BASE_ADDR + 0x2f8) // 0x314
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19 (SW_MUX_BASE_ADDR + 0x2fc) // 0x318
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20 (SW_MUX_BASE_ADDR + 0x300) // 0x31c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21 (SW_MUX_BASE_ADDR + 0x304) // 0x320
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22 (SW_MUX_BASE_ADDR + 0x308) // 0x324
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23 (SW_MUX_BASE_ADDR + 0x30c) // 0x328
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3 (SW_MUX_BASE_ADDR + 0x310) // 0x32c
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2 (SW_MUX_BASE_ADDR + 0x314) // 0x330
+#define IOMUXC_SW_MUX_CTL_PAD_DI_GP1 (SW_MUX_BASE_ADDR + 0x318) // 0x334
+#define IOMUXC_SW_MUX_CTL_PAD_DI_GP2 (SW_MUX_BASE_ADDR + 0x31c) // 0x338
+#define IOMUXC_SW_MUX_CTL_PAD_DI_GP3 (SW_MUX_BASE_ADDR + 0x320) // 0x33c
+#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4 (SW_MUX_BASE_ADDR + 0x324) // 0x340
+#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2 (SW_MUX_BASE_ADDR + 0x328) // 0x344
+#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3 (SW_MUX_BASE_ADDR + 0x32c) // 0x348
+#define IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK (SW_MUX_BASE_ADDR + 0x330) // 0x34c
+#define IOMUXC_SW_MUX_CTL_PAD_DI_GP4 (SW_MUX_BASE_ADDR + 0x334) // 0x350
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0 (SW_MUX_BASE_ADDR + 0x338) // 0x354
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1 (SW_MUX_BASE_ADDR + 0x33c) // 0x358
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2 (SW_MUX_BASE_ADDR + 0x340) // 0x35c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3 (SW_MUX_BASE_ADDR + 0x344) // 0x360
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4 (SW_MUX_BASE_ADDR + 0x348) // 0x364
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5 (SW_MUX_BASE_ADDR + 0x34c) // 0x368
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6 (SW_MUX_BASE_ADDR + 0x350) // 0x36c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7 (SW_MUX_BASE_ADDR + 0x354) // 0x370
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8 (SW_MUX_BASE_ADDR + 0x358) // 0x374
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9 (SW_MUX_BASE_ADDR + 0x35c) // 0x378
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10 (SW_MUX_BASE_ADDR + 0x360) // 0x37c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11 (SW_MUX_BASE_ADDR + 0x364) // 0x380
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12 (SW_MUX_BASE_ADDR + 0x368) // 0x384
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13 (SW_MUX_BASE_ADDR + 0x36c) // 0x388
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14 (SW_MUX_BASE_ADDR + 0x370) // 0x38c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15 (SW_MUX_BASE_ADDR + 0x374) // 0x390
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD (SW_MUX_BASE_ADDR + 0x378) // 0x394
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK (SW_MUX_BASE_ADDR + 0x37c) // 0x398
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 (SW_MUX_BASE_ADDR + 0x380) // 0x39c
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 (SW_MUX_BASE_ADDR + 0x384) // 0x3a0
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 (SW_MUX_BASE_ADDR + 0x388) // 0x3a4
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 (SW_MUX_BASE_ADDR + 0x38c) // 0x3a8
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_0 (SW_MUX_BASE_ADDR + 0x390) // 0x3ac
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_1 (SW_MUX_BASE_ADDR + 0x394) // 0x3b0
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD (SW_MUX_BASE_ADDR + 0x398) // 0x3b4
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK (SW_MUX_BASE_ADDR + 0x39c) // 0x3b8
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 (SW_MUX_BASE_ADDR + 0x3a0) // 0x3bc
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 (SW_MUX_BASE_ADDR + 0x3a4) // 0x3c0
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 (SW_MUX_BASE_ADDR + 0x3a8) // 0x3c4
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 (SW_MUX_BASE_ADDR + 0x3ac) // 0x3c8
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_2 (SW_MUX_BASE_ADDR + 0x3b0) // 0x3cc
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_3 (SW_MUX_BASE_ADDR + 0x3b4) // 0x3d0
+#define IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ (SW_MUX_BASE_ADDR + 0x3b8) // 0x3d4
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_4 (SW_MUX_BASE_ADDR + 0x3bc) // 0x3d8
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_5 (SW_MUX_BASE_ADDR + 0x3c0) // 0x3dc
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_6 (SW_MUX_BASE_ADDR + 0x3c4) // 0x3e0
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_7 (SW_MUX_BASE_ADDR + 0x3c8) // 0x3e4
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_8 (SW_MUX_BASE_ADDR + 0x3cc) // 0x3e8
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_9 (SW_MUX_BASE_ADDR + 0x3d0) // 0x3ec
+
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D16 (SW_PAD_BASE_ADDR + 0x0) // 0x3f0
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D17 (SW_PAD_BASE_ADDR + 0x4) // 0x3f4
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D18 (SW_PAD_BASE_ADDR + 0x8) // 0x3f8
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D19 (SW_PAD_BASE_ADDR + 0xc) // 0x3fc
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D20 (SW_PAD_BASE_ADDR + 0x10) // 0x400
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D21 (SW_PAD_BASE_ADDR + 0x14) // 0x404
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D22 (SW_PAD_BASE_ADDR + 0x18) // 0x408
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D23 (SW_PAD_BASE_ADDR + 0x1c) // 0x40c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D24 (SW_PAD_BASE_ADDR + 0x20) // 0x410
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D25 (SW_PAD_BASE_ADDR + 0x24) // 0x414
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D26 (SW_PAD_BASE_ADDR + 0x28) // 0x418
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D27 (SW_PAD_BASE_ADDR + 0x2c) // 0x41c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D28 (SW_PAD_BASE_ADDR + 0x30) // 0x420
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D29 (SW_PAD_BASE_ADDR + 0x34) // 0x424
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D30 (SW_PAD_BASE_ADDR + 0x38) // 0x428
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D31 (SW_PAD_BASE_ADDR + 0x3c) // 0x42c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A16 (SW_PAD_BASE_ADDR + 0x40) // 0x430
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A17 (SW_PAD_BASE_ADDR + 0x44) // 0x434
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A18 (SW_PAD_BASE_ADDR + 0x48) // 0x438
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A19 (SW_PAD_BASE_ADDR + 0x4c) // 0x43c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A20 (SW_PAD_BASE_ADDR + 0x50) // 0x440
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A21 (SW_PAD_BASE_ADDR + 0x54) // 0x444
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A22 (SW_PAD_BASE_ADDR + 0x58) // 0x448
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A23 (SW_PAD_BASE_ADDR + 0x5c) // 0x44c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A24 (SW_PAD_BASE_ADDR + 0x60) // 0x450
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A25 (SW_PAD_BASE_ADDR + 0x64) // 0x454
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A26 (SW_PAD_BASE_ADDR + 0x68) // 0x458
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A27 (SW_PAD_BASE_ADDR + 0x6c) // 0x45c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 (SW_PAD_BASE_ADDR + 0x70) // 0x460
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 (SW_PAD_BASE_ADDR + 0x74) // 0x464
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 (SW_PAD_BASE_ADDR + 0x78) // 0x468
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 (SW_PAD_BASE_ADDR + 0x7c) // 0x46c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE (SW_PAD_BASE_ADDR + 0x80) // 0x470
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 (SW_PAD_BASE_ADDR + 0x84) // 0x474
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 (SW_PAD_BASE_ADDR + 0x88) // 0x478
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS2 (SW_PAD_BASE_ADDR + 0x8c) // 0x47c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS3 (SW_PAD_BASE_ADDR + 0x90) // 0x480
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS4 (SW_PAD_BASE_ADDR + 0x94) // 0x484
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS5 (SW_PAD_BASE_ADDR + 0x98) // 0x488
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK (SW_PAD_BASE_ADDR + 0x9c) // 0x48c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT (SW_PAD_BASE_ADDR + 0xa0) // 0x490
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA (SW_PAD_BASE_ADDR + 0xa4) // 0x494
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK (SW_PAD_BASE_ADDR + 0xa8) // 0x498
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW (SW_PAD_BASE_ADDR + 0xac) // 0x49c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CRE (SW_PAD_BASE_ADDR + 0xb0) // 0x4a0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS (SW_PAD_BASE_ADDR + 0xb4) // 0x4a4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS (SW_PAD_BASE_ADDR + 0xb8) // 0x4a8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE (SW_PAD_BASE_ADDR + 0xbc) // 0x4ac
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 (SW_PAD_BASE_ADDR + 0xc0) // 0x4b0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 (SW_PAD_BASE_ADDR + 0xc4) // 0x4b4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK (SW_PAD_BASE_ADDR + 0xc8) // 0x4b8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 (SW_PAD_BASE_ADDR + 0xcc) // 0x4bc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 (SW_PAD_BASE_ADDR + 0xd0) // 0x4c0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 (SW_PAD_BASE_ADDR + 0xd4) // 0x4c4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 (SW_PAD_BASE_ADDR + 0xd8) // 0x4c8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 (SW_PAD_BASE_ADDR + 0xdc) // 0x4cc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 (SW_PAD_BASE_ADDR + 0xe0) // 0x4d0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 (SW_PAD_BASE_ADDR + 0xe4) // 0x4d4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 (SW_PAD_BASE_ADDR + 0xe8) // 0x4d8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 (SW_PAD_BASE_ADDR + 0xec) // 0x4dc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 (SW_PAD_BASE_ADDR + 0xf0) // 0x4e0
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B (SW_PAD_BASE_ADDR + 0xf4) // 0x4e4
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B (SW_PAD_BASE_ADDR + 0xf8) // 0x4e8
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE (SW_PAD_BASE_ADDR + 0xfc) // 0x4ec
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE (SW_PAD_BASE_ADDR + 0x100) // 0x4f0
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B (SW_PAD_BASE_ADDR + 0x104) // 0x4f4
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 (SW_PAD_BASE_ADDR + 0x108) // 0x4f8
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 (SW_PAD_BASE_ADDR + 0x10c) // 0x4fc
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 (SW_PAD_BASE_ADDR + 0x110) // 0x500
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 (SW_PAD_BASE_ADDR + 0x114) // 0x504
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2 (SW_PAD_BASE_ADDR + 0x118) // 0x508
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1 (SW_PAD_BASE_ADDR + 0x11c) // 0x50c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0 (SW_PAD_BASE_ADDR + 0x120) // 0x510
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND (SW_PAD_BASE_ADDR + 0x124) // 0x514
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 (SW_PAD_BASE_ADDR + 0x128) // 0x518
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 (SW_PAD_BASE_ADDR + 0x12c) // 0x51c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 (SW_PAD_BASE_ADDR + 0x130) // 0x520
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 (SW_PAD_BASE_ADDR + 0x134) // 0x524
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 (SW_PAD_BASE_ADDR + 0x138) // 0x528
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 (SW_PAD_BASE_ADDR + 0x13c) // 0x52c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 (SW_PAD_BASE_ADDR + 0x140) // 0x530
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 (SW_PAD_BASE_ADDR + 0x144) // 0x534
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT (SW_PAD_BASE_ADDR + 0x148) // 0x538
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 (SW_PAD_BASE_ADDR + 0x14c) // 0x53c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 (SW_PAD_BASE_ADDR + 0x150) // 0x540
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 (SW_PAD_BASE_ADDR + 0x154) // 0x544
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 (SW_PAD_BASE_ADDR + 0x158) // 0x548
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 (SW_PAD_BASE_ADDR + 0x15c) // 0x54c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 (SW_PAD_BASE_ADDR + 0x160) // 0x550
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 (SW_PAD_BASE_ADDR + 0x164) // 0x554
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 (SW_PAD_BASE_ADDR + 0x168) // 0x558
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 (SW_PAD_BASE_ADDR + 0x16c) // 0x55c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 (SW_PAD_BASE_ADDR + 0x170) // 0x560
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 (SW_PAD_BASE_ADDR + 0x174) // 0x564
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 (SW_PAD_BASE_ADDR + 0x178) // 0x568
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 (SW_PAD_BASE_ADDR + 0x17c) // 0x56c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 (SW_PAD_BASE_ADDR + 0x180) // 0x570
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 (SW_PAD_BASE_ADDR + 0x184) // 0x574
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 (SW_PAD_BASE_ADDR + 0x188) // 0x578
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D8 (SW_PAD_BASE_ADDR + 0x18c) // 0x57c
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D9 (SW_PAD_BASE_ADDR + 0x190) // 0x580
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D10 (SW_PAD_BASE_ADDR + 0x194) // 0x584
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D11 (SW_PAD_BASE_ADDR + 0x198) // 0x588
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D12 (SW_PAD_BASE_ADDR + 0x19c) // 0x58c
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D13 (SW_PAD_BASE_ADDR + 0x1a0) // 0x590
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D14 (SW_PAD_BASE_ADDR + 0x1a4) // 0x594
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D15 (SW_PAD_BASE_ADDR + 0x1a8) // 0x598
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D16 (SW_PAD_BASE_ADDR + 0x1ac) // 0x59c
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D17 (SW_PAD_BASE_ADDR + 0x1b0) // 0x5a0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D18 (SW_PAD_BASE_ADDR + 0x1b4) // 0x5a4
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D19 (SW_PAD_BASE_ADDR + 0x1b8) // 0x5a8
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC (SW_PAD_BASE_ADDR + 0x1bc) // 0x5ac
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC (SW_PAD_BASE_ADDR + 0x1c0) // 0x5b0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK (SW_PAD_BASE_ADDR + 0x1c4) // 0x5b4
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK (SW_PAD_BASE_ADDR + 0x1c8) // 0x5b8
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D12 (SW_PAD_BASE_ADDR + 0x1cc) // 0x5bc
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D13 (SW_PAD_BASE_ADDR + 0x1d0) // 0x5c0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D14 (SW_PAD_BASE_ADDR + 0x1d4) // 0x5c4
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D15 (SW_PAD_BASE_ADDR + 0x1d8) // 0x5c8
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D16 (SW_PAD_BASE_ADDR + 0x1dc) // 0x5cc
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D17 (SW_PAD_BASE_ADDR + 0x1e0) // 0x5d0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D18 (SW_PAD_BASE_ADDR + 0x1e4) // 0x5d4
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D19 (SW_PAD_BASE_ADDR + 0x1e8) // 0x5d8
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC (SW_PAD_BASE_ADDR + 0x1ec) // 0x5dc
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC (SW_PAD_BASE_ADDR + 0x1f0) // 0x5e0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK (SW_PAD_BASE_ADDR + 0x1f4) // 0x5e4
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK (SW_PAD_BASE_ADDR + 0x1f8) // 0x5e8
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT (SW_PAD_BASE_ADDR + 0x1fc) // 0x5ec
+#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD (SW_PAD_BASE_ADDR + 0x200) // 0x5f0
+#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD (SW_PAD_BASE_ADDR + 0x204) // 0x5f4
+#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK (SW_PAD_BASE_ADDR + 0x208) // 0x5f8
+#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS (SW_PAD_BASE_ADDR + 0x20c) // 0x5fc
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI (SW_PAD_BASE_ADDR + 0x210) // 0x600
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO (SW_PAD_BASE_ADDR + 0x214) // 0x604
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 (SW_PAD_BASE_ADDR + 0x218) // 0x608
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 (SW_PAD_BASE_ADDR + 0x21c) // 0x60c
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY (SW_PAD_BASE_ADDR + 0x220) // 0x610
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK (SW_PAD_BASE_ADDR + 0x224) // 0x614
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD (SW_PAD_BASE_ADDR + 0x228) // 0x618
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD (SW_PAD_BASE_ADDR + 0x22c) // 0x61c
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS (SW_PAD_BASE_ADDR + 0x230) // 0x620
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS (SW_PAD_BASE_ADDR + 0x234) // 0x624
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD (SW_PAD_BASE_ADDR + 0x238) // 0x628
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD (SW_PAD_BASE_ADDR + 0x23c) // 0x62c
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD (SW_PAD_BASE_ADDR + 0x240) // 0x630
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD (SW_PAD_BASE_ADDR + 0x244) // 0x634
+#define IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE (SW_PAD_BASE_ADDR + 0x248) // 0x638
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 (SW_PAD_BASE_ADDR + 0x24c) // 0x63c
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 (SW_PAD_BASE_ADDR + 0x250) // 0x640
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 (SW_PAD_BASE_ADDR + 0x254) // 0x644
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 (SW_PAD_BASE_ADDR + 0x258) // 0x648
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 (SW_PAD_BASE_ADDR + 0x25c) // 0x64c
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 (SW_PAD_BASE_ADDR + 0x260) // 0x650
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 (SW_PAD_BASE_ADDR + 0x264) // 0x654
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 (SW_PAD_BASE_ADDR + 0x268) // 0x658
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 (SW_PAD_BASE_ADDR + 0x26c) // 0x65c
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL5 (SW_PAD_BASE_ADDR + 0x270) // 0x660
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK (SW_PAD_BASE_ADDR + 0x274) // 0x664
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS (SW_PAD_BASE_ADDR + 0x278) // 0x668
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI (SW_PAD_BASE_ADDR + 0x27c) // 0x66c
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB (SW_PAD_BASE_ADDR + 0x280) // 0x670
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD (SW_PAD_BASE_ADDR + 0x284) // 0x674
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK (SW_PAD_BASE_ADDR + 0x288) // 0x678
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR (SW_PAD_BASE_ADDR + 0x28c) // 0x67c
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_STP (SW_PAD_BASE_ADDR + 0x290) // 0x680
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT (SW_PAD_BASE_ADDR + 0x294) // 0x684
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0 (SW_PAD_BASE_ADDR + 0x298) // 0x688
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1 (SW_PAD_BASE_ADDR + 0x29c) // 0x68c
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2 (SW_PAD_BASE_ADDR + 0x2a0) // 0x690
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3 (SW_PAD_BASE_ADDR + 0x2a4) // 0x694
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4 (SW_PAD_BASE_ADDR + 0x2a8) // 0x698
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5 (SW_PAD_BASE_ADDR + 0x2ac) // 0x69c
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6 (SW_PAD_BASE_ADDR + 0x2b0) // 0x6a0
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7 (SW_PAD_BASE_ADDR + 0x2b4) // 0x6a4
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 (SW_PAD_BASE_ADDR + 0x2b8) // 0x6a8
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12 (SW_PAD_BASE_ADDR + 0x2bc) // 0x6ac
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13 (SW_PAD_BASE_ADDR + 0x2c0) // 0x6b0
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS (SW_PAD_BASE_ADDR + 0x2c4) // 0x6b4
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS (SW_PAD_BASE_ADDR + 0x2c8) // 0x6b8
+#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN (SW_PAD_BASE_ADDR + 0x2cc) // 0x6bc
+#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO (SW_PAD_BASE_ADDR + 0x2d0) // 0x6c0
+#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK (SW_PAD_BASE_ADDR + 0x2d4) // 0x6c4
+#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS (SW_PAD_BASE_ADDR + 0x2d8) // 0x6c8
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0 (SW_PAD_BASE_ADDR + 0x2dc) // 0x6cc
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1 (SW_PAD_BASE_ADDR + 0x2e0) // 0x6d0
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2 (SW_PAD_BASE_ADDR + 0x2e4) // 0x6d4
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3 (SW_PAD_BASE_ADDR + 0x2e8) // 0x6d8
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4 (SW_PAD_BASE_ADDR + 0x2ec) // 0x6dc
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5 (SW_PAD_BASE_ADDR + 0x2f0) // 0x6e0
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6 (SW_PAD_BASE_ADDR + 0x2f4) // 0x6e4
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7 (SW_PAD_BASE_ADDR + 0x2f8) // 0x6e8
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8 (SW_PAD_BASE_ADDR + 0x2fc) // 0x6ec
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9 (SW_PAD_BASE_ADDR + 0x300) // 0x6f0
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10 (SW_PAD_BASE_ADDR + 0x304) // 0x6f4
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11 (SW_PAD_BASE_ADDR + 0x308) // 0x6f8
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12 (SW_PAD_BASE_ADDR + 0x30c) // 0x6fc
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13 (SW_PAD_BASE_ADDR + 0x310) // 0x700
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14 (SW_PAD_BASE_ADDR + 0x314) // 0x704
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15 (SW_PAD_BASE_ADDR + 0x318) // 0x708
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16 (SW_PAD_BASE_ADDR + 0x31c) // 0x70c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17 (SW_PAD_BASE_ADDR + 0x320) // 0x710
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18 (SW_PAD_BASE_ADDR + 0x324) // 0x714
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19 (SW_PAD_BASE_ADDR + 0x328) // 0x718
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20 (SW_PAD_BASE_ADDR + 0x32c) // 0x71c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21 (SW_PAD_BASE_ADDR + 0x330) // 0x720
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22 (SW_PAD_BASE_ADDR + 0x334) // 0x724
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23 (SW_PAD_BASE_ADDR + 0x338) // 0x728
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3 (SW_PAD_BASE_ADDR + 0x33c) // 0x72c
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK (SW_PAD_BASE_ADDR + 0x340) // 0x730
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2 (SW_PAD_BASE_ADDR + 0x344) // 0x734
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15 (SW_PAD_BASE_ADDR + 0x348) // 0x738
+#define IOMUXC_SW_PAD_CTL_PAD_DI_GP1 (SW_PAD_BASE_ADDR + 0x34c) // 0x73c
+#define IOMUXC_SW_PAD_CTL_PAD_DI_GP2 (SW_PAD_BASE_ADDR + 0x350) // 0x740
+#define IOMUXC_SW_PAD_CTL_PAD_DI_GP3 (SW_PAD_BASE_ADDR + 0x354) // 0x744
+#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4 (SW_PAD_BASE_ADDR + 0x358) // 0x748
+#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2 (SW_PAD_BASE_ADDR + 0x35c) // 0x74c
+#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3 (SW_PAD_BASE_ADDR + 0x360) // 0x750
+#define IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK (SW_PAD_BASE_ADDR + 0x364) // 0x754
+#define IOMUXC_SW_PAD_CTL_PAD_DI_GP4 (SW_PAD_BASE_ADDR + 0x368) // 0x758
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0 (SW_PAD_BASE_ADDR + 0x36c) // 0x75c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1 (SW_PAD_BASE_ADDR + 0x370) // 0x760
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2 (SW_PAD_BASE_ADDR + 0x374) // 0x764
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3 (SW_PAD_BASE_ADDR + 0x378) // 0x768
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4 (SW_PAD_BASE_ADDR + 0x37c) // 0x76c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5 (SW_PAD_BASE_ADDR + 0x380) // 0x770
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6 (SW_PAD_BASE_ADDR + 0x384) // 0x774
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7 (SW_PAD_BASE_ADDR + 0x388) // 0x778
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8 (SW_PAD_BASE_ADDR + 0x38c) // 0x77c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9 (SW_PAD_BASE_ADDR + 0x390) // 0x780
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10 (SW_PAD_BASE_ADDR + 0x394) // 0x784
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11 (SW_PAD_BASE_ADDR + 0x398) // 0x788
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12 (SW_PAD_BASE_ADDR + 0x39c) // 0x78c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13 (SW_PAD_BASE_ADDR + 0x3a0) // 0x790
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14 (SW_PAD_BASE_ADDR + 0x3a4) // 0x794
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15 (SW_PAD_BASE_ADDR + 0x3a8) // 0x798
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD (SW_PAD_BASE_ADDR + 0x3ac) // 0x79c
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK (SW_PAD_BASE_ADDR + 0x3b0) // 0x7a0
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 (SW_PAD_BASE_ADDR + 0x3b4) // 0x7a4
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 (SW_PAD_BASE_ADDR + 0x3b8) // 0x7a8
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 (SW_PAD_BASE_ADDR + 0x3bc) // 0x7ac
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 (SW_PAD_BASE_ADDR + 0x3c0) // 0x7b0
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_0 (SW_PAD_BASE_ADDR + 0x3c4) // 0x7b4
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_1 (SW_PAD_BASE_ADDR + 0x3c8) // 0x7b8
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD (SW_PAD_BASE_ADDR + 0x3cc) // 0x7bc
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK (SW_PAD_BASE_ADDR + 0x3d0) // 0x7c0
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 (SW_PAD_BASE_ADDR + 0x3d4) // 0x7c4
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 (SW_PAD_BASE_ADDR + 0x3d8) // 0x7c8
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 (SW_PAD_BASE_ADDR + 0x3dc) // 0x7cc
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 (SW_PAD_BASE_ADDR + 0x3e0) // 0x7d0
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_2 (SW_PAD_BASE_ADDR + 0x3e4) // 0x7d4
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_3 (SW_PAD_BASE_ADDR + 0x3e8) // 0x7d8
+#define IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B (SW_PAD_BASE_ADDR + 0x3ec) // 0x7dc
+#define IOMUXC_SW_PAD_CTL_PAD_POR_B (SW_PAD_BASE_ADDR + 0x3f0) // 0x7e0
+#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 (SW_PAD_BASE_ADDR + 0x3f4) // 0x7e4
+#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 (SW_PAD_BASE_ADDR + 0x3f8) // 0x7e8
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY (SW_PAD_BASE_ADDR + 0x3fc) // 0x7ec
+#define IOMUXC_SW_PAD_CTL_PAD_CKIL (SW_PAD_BASE_ADDR + 0x400) // 0x7f0
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ (SW_PAD_BASE_ADDR + 0x404) // 0x7f4
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ (SW_PAD_BASE_ADDR + 0x408) // 0x7f8
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ (SW_PAD_BASE_ADDR + 0x40c) // 0x7fc
+#define IOMUXC_SW_PAD_CTL_PAD_CLK_SS (SW_PAD_BASE_ADDR + 0x410) // 0x800
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_4 (SW_PAD_BASE_ADDR + 0x414) // 0x804
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_5 (SW_PAD_BASE_ADDR + 0x418) // 0x808
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_6 (SW_PAD_BASE_ADDR + 0x41c) // 0x80c
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_7 (SW_PAD_BASE_ADDR + 0x420) // 0x810
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_8 (SW_PAD_BASE_ADDR + 0x424) // 0x814
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_9 (SW_PAD_BASE_ADDR + 0x428) // 0x818
+
+#define IOMUXC_SW_PAD_CTL_GRP_CSI2_PKE0 (SW_GRP_BASE_ADDR + 0x0) // 0x81c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPKS (SW_GRP_BASE_ADDR + 0x4) // 0x820
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR1 (SW_GRP_BASE_ADDR + 0x8) // 0x824
+#define IOMUXC_SW_PAD_CTL_GRP_DISP2_PKE0 (SW_GRP_BASE_ADDR + 0xc) // 0x828
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B4 (SW_GRP_BASE_ADDR + 0x10) // 0x82c
+#define IOMUXC_SW_PAD_CTL_GRP_INDDR (SW_GRP_BASE_ADDR + 0x14) // 0x830
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR2 (SW_GRP_BASE_ADDR + 0x18) // 0x834
+#define IOMUXC_SW_PAD_CTL_GRP_PKEDDR (SW_GRP_BASE_ADDR + 0x1c) // 0x838
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_A0 (SW_GRP_BASE_ADDR + 0x20) // 0x83c
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_PKE0 (SW_GRP_BASE_ADDR + 0x24) // 0x840
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR3 (SW_GRP_BASE_ADDR + 0x28) // 0x844
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_A1 (SW_GRP_BASE_ADDR + 0x2c) // 0x848
+#define IOMUXC_SW_PAD_CTL_GRP_DDRAPUS (SW_GRP_BASE_ADDR + 0x30) // 0x84c
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR4 (SW_GRP_BASE_ADDR + 0x34) // 0x850
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR5 (SW_GRP_BASE_ADDR + 0x38) // 0x854
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR6 (SW_GRP_BASE_ADDR + 0x3c) // 0x858
+#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR0 (SW_GRP_BASE_ADDR + 0x40) // 0x85c
+#define IOMUXC_SW_PAD_CTL_GRP_CSI1_PKE0 (SW_GRP_BASE_ADDR + 0x44) // 0x860
+#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR1 (SW_GRP_BASE_ADDR + 0x48) // 0x864
+#define IOMUXC_SW_PAD_CTL_GRP_DISP1_PKE0 (SW_GRP_BASE_ADDR + 0x4c) // 0x868
+#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR2 (SW_GRP_BASE_ADDR + 0x50) // 0x86c
+#define IOMUXC_SW_PAD_CTL_GRP_HVDDR (SW_GRP_BASE_ADDR + 0x54) // 0x870
+#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR3 (SW_GRP_BASE_ADDR + 0x58) // 0x874
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B0 (SW_GRP_BASE_ADDR + 0x5c) // 0x878
+#define IOMUXC_SW_PAD_CTL_GRP_DDRAPKS (SW_GRP_BASE_ADDR + 0x60) // 0x87c
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B1 (SW_GRP_BASE_ADDR + 0x64) // 0x880
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPUS (SW_GRP_BASE_ADDR + 0x68) // 0x884
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS1 (SW_GRP_BASE_ADDR + 0x6c) // 0x888
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B2 (SW_GRP_BASE_ADDR + 0x70) // 0x88c
+#define IOMUXC_SW_PAD_CTL_GRP_PKEADDR (SW_GRP_BASE_ADDR + 0x74) // 0x890
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS2 (SW_GRP_BASE_ADDR + 0x78) // 0x894
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS3 (SW_GRP_BASE_ADDR + 0x7c) // 0x898
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B4 (SW_GRP_BASE_ADDR + 0x80) // 0x89c
+#define IOMUXC_SW_PAD_CTL_GRP_INMODE1 (SW_GRP_BASE_ADDR + 0x84) // 0x8a0
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B0 (SW_GRP_BASE_ADDR + 0x88) // 0x8a4
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS4 (SW_GRP_BASE_ADDR + 0x8c) // 0x8a8
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B1 (SW_GRP_BASE_ADDR + 0x90) // 0x8ac
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A0 (SW_GRP_BASE_ADDR + 0x94) // 0x8b0
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS5 (SW_GRP_BASE_ADDR + 0x98) // 0x8b4
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B2 (SW_GRP_BASE_ADDR + 0x9c) // 0x8b8
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A1 (SW_GRP_BASE_ADDR + 0xa0) // 0x8bc
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS6 (SW_GRP_BASE_ADDR + 0xa4) // 0x8c0
+
+#define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x0) // 0x8c4
+#define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x4) // 0x8c8
+#define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x8) // 0x8cc
+#define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc) // 0x8d0
+#define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x10) // 0x8d4
+#define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x14) // 0x8d8
+#define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x18) // 0x8dc
+#define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x1c) // 0x8e0
+#define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x20) // 0x8e4
+#define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x24) // 0x8e8
+#define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x28) // 0x8ec
+#define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x2c) // 0x8f0
+#define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x30) // 0x8f4
+#define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x34) // 0x8f8
+#define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x38) // 0x8fc
+#define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x3c) // 0x900
+#define IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x40) // 0x904
+#define IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x44) // 0x908
+#define IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x48) // 0x90c
+#define IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x4c) // 0x910
+#define IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x50) // 0x914
+#define IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x54) // 0x918
+#define IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x58) // 0x91c
+#define IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x5c) // 0x920
+#define IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x60) // 0x924
+#define IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x64) // 0x928
+#define IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x68) // 0x92c
+#define IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x6c) // 0x930
+#define IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x70) // 0x934
+#define IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x74) // 0x938
+#define IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x78) // 0x93c
+#define IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x7c) // 0x940
+#define IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x80) // 0x944
+#define IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x84) // 0x948
+#define IOMUXC_FEC_FEC_COL_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x88) // 0x94c
+#define IOMUXC_FEC_FEC_CRS_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x8c) // 0x950
+#define IOMUXC_FEC_FEC_MDI_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x90) // 0x954
+#define IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x94) // 0x958
+#define IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x98) // 0x95c
+#define IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x9c) // 0x960
+#define IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xa0) // 0x964
+#define IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xa4) // 0x968
+#define IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xa8) // 0x96c
+#define IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xac) // 0x970
+#define IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xb0) // 0x974
+#define IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xb4) // 0x978
+#define IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xb8) // 0x97c
+#define IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xbc) // 0x980
+#define IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc0) // 0x984
+#define IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc4) // 0x988
+#define IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc8) // 0x98c
+#define IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xcc) // 0x990
+#define IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xd0) // 0x994
+#define IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xd4) // 0x998
+#define IOMUXC_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xd8) // 0x99c
+#define IOMUXC_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xdc) // 0x9a0
+#define IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xe0) // 0x9a4
+#define IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xe4) // 0x9a8
+#define IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xe8) // 0x9ac
+#define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xec) // 0x9b0
+#define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xf0) // 0x9b4
+#define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xf4) // 0x9b8
+#define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xf8) // 0x9bc
+#define IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xfc) // 0x9c0
+#define IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x100) // 0x9c4
+#define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x104) // 0x9c8
+#define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x108) // 0x9cc
+#define IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x10c) // 0x9d0
+#define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x110) // 0x9d4
+#define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x114) // 0x9d8
+#define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x118) // 0x9dc
+#define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x11c) // 0x9e0
+#define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x120) // 0x9e4
+#define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x124) // 0x9e8
+#define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x128) // 0x9ec
+#define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x12c) // 0x9f0
+#define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x130) // 0x9f4
+#define IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x134) // 0x9f8
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x138) // 0x9fc
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x13c) // 0xa00
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x140) // 0xa04
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x144) // 0xa08
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x148) // 0xa0c
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x14c) // 0xa10
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x150) // 0xa14
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x154) // 0xa18
+#define IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x158) // 0xa1c
+#define IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x15c) // 0xa20
+#define IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x160) // 0xa24
+
+#define IOMUX_SW_MUX_CTL_SION 0x4
+
+#define IOMUX_PAD_SRC_LSH 0
+#define IOMUX_PAD_DSE_LSH 1
+#define IOMUX_PAD_PUE_LSH 6
+#define IOMUX_PAD_HYS_LSH 8
+
+// IOMUXC_SW_PAD_CTL, value of each field
+#define IOMUX_SW_PAD_CTL_SRE_SLOW 0 // Slow slew rate
+#define IOMUX_SW_PAD_CTL_SRE_FAST 1 // Fast slew rate
+
+#define IOMUX_SW_PAD_CTL_DSE_NORMAL 0 // Normal drive strength
+#define IOMUX_SW_PAD_CTL_DSE_MEDIUM 1 // Medium drive strength
+#define IOMUX_SW_PAD_CTL_DSE_HIGH 2 // High drive strength
+#define IOMUX_SW_PAD_CTL_DSE_MAX 3 // Maximum drive strength
+
+#define IOMUX_SW_PAD_CTL_ODE_DISABLE 0 // Disable open drain
+#define IOMUX_SW_PAD_CTL_ODE_ENABLE 1 // Enable open drain
+
+#define IOMUX_SW_PAD_CTL_PUS_100K_DOWN 0 // 100K Ohm pull down
+#define IOMUX_SW_PAD_CTL_PUS_47K_UP 1 // 47K Ohm pull up
+#define IOMUX_SW_PAD_CTL_PUS_100K_UP 2 // 100K Ohm pull up
+#define IOMUX_SW_PAD_CTL_PUS_22K_UP 3 // 22K Ohm pull up
+
+#define IOMUX_SW_PAD_CTL_PUE_KEEPER 0 // Keeper enable
+#define IOMUX_SW_PAD_CTL_PUE_PULL 1 // Pull up/down enable
+
+#define IOMUX_SW_PAD_CTL_PKE_DISABLE 0 // Pull up/down/keeper disabled
+#define IOMUX_SW_PAD_CTL_PKE_ENABLE 1 // Pull up/down/keeper enabled
+
+#define IOMUX_SW_PAD_CTL_HYS_DISABLE 0 // Disable hysteresis
+#define IOMUX_SW_PAD_CTL_HYS_ENABLE 1 // Enable hysteresis
+
+#define IOMUX_SW_PAD_CTL_DDR_INPUT_CMOS 0 // CMOS input
+#define IOMUX_SW_PAD_CTL_DDR_INPUT_DDR 1 // DDR input
+
+#define IOMUX_SW_PAD_CTL_HVE_LOW 0 // Low output voltage
+#define IOMUX_SW_PAD_CTL_HVE_HIGH 1 // High output voltage
+// offset
+#define IOMUX_SW_PAD_CTL_SRE_LSH 0
+#define IOMUX_SW_PAD_CTL_DSE_LSH 1
+#define IOMUX_SW_PAD_CTL_ODE_LSH 3
+#define IOMUX_SW_PAD_CTL_PUS_LSH 4
+#define IOMUX_SW_PAD_CTL_PUE_LSH 6
+#define IOMUX_SW_PAD_CTL_PKE_LSH 7
+#define IOMUX_SW_PAD_CTL_HYS_LSH 8
+#define IOMUX_SW_PAD_CTL_DDR_INPUT_LSH 9
+#define IOMUX_SW_PAD_CTL_HVE_LSH 13
+// end of pad control configuration
+
+// Mode define
+typedef enum
+{
+ IOMUX_SW_MUX_CTL_ALT0 = 0,
+ IOMUX_SW_MUX_CTL_ALT1 = 1,
+ IOMUX_SW_MUX_CTL_ALT2 = 2,
+ IOMUX_SW_MUX_CTL_ALT3 = 3,
+ IOMUX_SW_MUX_CTL_ALT4 = 4,
+ IOMUX_SW_MUX_CTL_ALT5 = 5,
+ IOMUX_SW_MUX_CTL_ALT6 = 6,
+ IOMUX_SW_MUX_CTL_ALT7 = 7
+} IOMUX_PIN_MODE;
+
+typedef enum
+{
+ IOMUX_PIN_SION_REGULAR = (0 << IOMUX_SW_MUX_CTL_SION),
+ IOMUX_PIN_SION_FORCE = (1 << IOMUX_SW_MUX_CTL_SION)
+} IOMUX_PIN_SION;
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_SLEW
+//
+// Specifies the slew rate for a pad.
+//
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_SLEW_SLOW = (IOMUX_SW_PAD_CTL_SRE_SLOW << IOMUX_SW_PAD_CTL_SRE_LSH),
+ IOMUX_PAD_SLEW_FAST = (IOMUX_SW_PAD_CTL_SRE_FAST << IOMUX_SW_PAD_CTL_SRE_LSH),
+} IOMUX_PAD_SLEW;
+
+#define IOMUX_PAD_SLEW_NULL ((IOMUX_PAD_SLEW)0)
+
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_DRIVE
+//
+// Specifies the drive strength for a pad.
+//
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_DRIVE_NORMAL = (IOMUX_SW_PAD_CTL_DSE_NORMAL << IOMUX_SW_PAD_CTL_DSE_LSH),
+ IOMUX_PAD_DRIVE_MEDIUM = (IOMUX_SW_PAD_CTL_DSE_MEDIUM << IOMUX_SW_PAD_CTL_DSE_LSH),
+ IOMUX_PAD_DRIVE_HIGH = (IOMUX_SW_PAD_CTL_DSE_HIGH << IOMUX_SW_PAD_CTL_DSE_LSH),
+ IOMUX_PAD_DRIVE_MAX = (IOMUX_SW_PAD_CTL_DSE_MAX << IOMUX_SW_PAD_CTL_DSE_LSH)
+} IOMUX_PAD_DRIVE;
+
+#define IOMUX_PAD_DRIVE_NULL ((IOMUX_PAD_DRIVE)0)
+
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_OPENDRAIN
+//
+// Specifies the open drain for a pad.
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_OPENDRAIN_DISABLE = (IOMUX_SW_PAD_CTL_ODE_DISABLE << IOMUX_SW_PAD_CTL_ODE_LSH),
+ IOMUX_PAD_OPENDRAIN_ENABLE = (IOMUX_SW_PAD_CTL_ODE_ENABLE << IOMUX_SW_PAD_CTL_ODE_LSH)
+} IOMUX_PAD_OPENDRAIN;
+
+#define IOMUX_PAD_OPENDRAIN_NULL ((IOMUX_PAD_OPENDRAIN)0)
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_PULL
+//
+// Specifies the pull-up/pull-down/keeper configuration for a pad.
+//
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_PULL_NONE = (IOMUX_SW_PAD_CTL_PKE_DISABLE << IOMUX_SW_PAD_CTL_PKE_LSH),
+
+ IOMUX_PAD_PULL_KEEPER = (IOMUX_SW_PAD_CTL_PUE_KEEPER << IOMUX_SW_PAD_CTL_PUE_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH),
+
+ IOMUX_PAD_PULL_DOWN_100K = (IOMUX_SW_PAD_CTL_PUS_100K_DOWN << IOMUX_SW_PAD_CTL_PUS_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) |
+ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH),
+
+ IOMUX_PAD_PULL_UP_100K = (IOMUX_SW_PAD_CTL_PUS_100K_UP << IOMUX_SW_PAD_CTL_PUS_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) |
+ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH),
+
+ IOMUX_PAD_PULL_UP_47K = (IOMUX_SW_PAD_CTL_PUS_47K_UP << IOMUX_SW_PAD_CTL_PUS_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) |
+ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH),
+
+ IOMUX_PAD_PULL_UP_22K = (IOMUX_SW_PAD_CTL_PUS_22K_UP << IOMUX_SW_PAD_CTL_PUS_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) |
+ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH)
+
+} IOMUX_PAD_PULL;
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_HYSTERESIS
+//
+// Specifies the hysteresis for a pad.
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_HYSTERESIS_DISABLE = (IOMUX_SW_PAD_CTL_HYS_DISABLE << IOMUX_SW_PAD_CTL_HYS_LSH),
+ IOMUX_PAD_HYSTERESIS_ENABLE = (IOMUX_SW_PAD_CTL_HYS_ENABLE << IOMUX_SW_PAD_CTL_HYS_LSH)
+} IOMUX_PAD_HYSTERESIS;
+
+#define IOMUX_PAD_HYSTERESIS_NULL ((IOMUX_PAD_HYSTERESIS)0)
+
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_INMODE
+//
+// Specifies the input mode (DDR/CMOS) for a pad.
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_INMODE_CMOS = (IOMUX_SW_PAD_CTL_DDR_INPUT_CMOS << IOMUX_SW_PAD_CTL_DDR_INPUT_LSH),
+ IOMUX_PAD_INMODE_DDR = (IOMUX_SW_PAD_CTL_DDR_INPUT_DDR << IOMUX_SW_PAD_CTL_DDR_INPUT_LSH)
+} IOMUX_PAD_INMODE;
+
+#define IOMUX_PAD_INMODE_NULL ((IOMUX_PAD_INMODE)0)
+
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_OUTVOLT
+//
+// Specifies the output voltage for a pad.
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_OUTVOLT_LOW = (IOMUX_SW_PAD_CTL_HVE_LOW << IOMUX_SW_PAD_CTL_HVE_LSH),
+ IOMUX_PAD_OUTVOLT_HIGH = (IOMUX_SW_PAD_CTL_HVE_HIGH << IOMUX_SW_PAD_CTL_HVE_LSH)
+} IOMUX_PAD_OUTVOLT;
+
+#define IOMUX_PAD_OUTVOLT_NULL ((IOMUX_PAD_OUTVOLT)0)
+
+#define CONFIG_PIN(Reg_Addr, Val) *(volatile unsigned int *)Reg_Addr=Val
+#define CONFIG_DAISY_CHAIN(Reg_Addr, Val) *(volatile unsigned int *)Reg_Addr=Val
+#define CONFIG_PAD(Reg_Addr,Val) *(volatile unsigned int *)Reg_Addr=Val
+
+#endif